AON_TIMER Simulation Results

Tuesday July 16 2024 23:15:02 UTC

GitHub Revision: `aad711e1bc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 38297581588405771015102977205739484163575733999253050480227719508149669635625

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.410s	510.373us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.180s	1.188ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	485.390us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.940s	10.373ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.540s	425.004us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	597.499us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	485.390us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	425.004us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	411.966us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.220s	481.800us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.232m	55.792ms	50	50	100.00
V2	jump	aon_timer_jump	1.580s	587.340us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.019m	533.398ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.260s	476.229us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.050s	551.753us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.050s	551.753us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.180s	1.188ms	5	5	100.00
		aon_timer_csr_rw	1.330s	485.390us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	425.004us	5	5	100.00
		aon_timer_same_csr_outstanding	4.190s	2.828ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.180s	1.188ms	5	5	100.00
		aon_timer_csr_rw	1.330s	485.390us	20	20	100.00
		aon_timer_csr_aliasing	1.540s	425.004us	5	5	100.00
		aon_timer_same_csr_outstanding	4.190s	2.828ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	3.910s	8.400ms	5	5	100.00
		aon_timer_tl_intg_err	14.370s	8.542ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.370s	8.542ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.797m	1.052s	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.07	99.33	93.67	100.00	--	98.40	99.51	49.52

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

2.aon_timer_stress_all_with_rand_reset.55478562388120416547686784756520059557125710153653053192856144736714285495034
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1526238596 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1526238596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.aon_timer_stress_all_with_rand_reset.14921242816009912901505675826776494190487112556368332012892486848781144512142
Line 967, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 76578099882 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 76578099882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 3 failures.

6.aon_timer_stress_all.101468849217204602456034407583550175621140739895523876440009669538882105676131
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 44110468044 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 44110468044 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

25.aon_timer_stress_all.3280625983143751905480701142082491249910966196234740076490611536809434224404
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/25.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 16920337378 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16920337378 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.