AON_TIMER Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	615.325us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.050s	1.027ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	491.046us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.230s	13.516ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.600s	636.197us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	491.016us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	491.046us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	636.197us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.140s	461.225us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.320s	494.795us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.291m	54.803ms	50	50	100.00
V2	jump	aon_timer_jump	1.580s	594.446us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.000m	405.676ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.270s	477.020us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.400s	519.505us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.400s	519.505us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.050s	1.027ms	5	5	100.00
		aon_timer_csr_rw	1.330s	491.046us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	636.197us	5	5	100.00
		aon_timer_same_csr_outstanding	5.410s	2.579ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.050s	1.027ms	5	5	100.00
		aon_timer_csr_rw	1.330s	491.046us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	636.197us	5	5	100.00
		aon_timer_same_csr_outstanding	5.410s	2.579ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	10.450s	7.765ms	5	5	100.00
		aon_timer_tl_intg_err	14.540s	8.545ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.540s	8.545ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.748m	662.754ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.09	99.33	93.67	100.00	--	98.40	99.51	49.64

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.14413635083986668072840685358045027001587635198093487659170771236060379759596
Line 260, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 707388855 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 707388855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.aon_timer_stress_all_with_rand_reset.35131514396451887100866015302245961278025824386473419351556230096797536973862
Line 362, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6505822810 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6505822810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 2 failures.

27.aon_timer_stress_all.25029998011197560324207966721654157801955972650196526089408584345127966448200
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1978855144 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1978855144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.aon_timer_stress_all.6519327685972157168970384957615871193148419652733098596665819568022231177340
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/37.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 115394474325 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 115394474325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---