AON_TIMER Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: `974aaab627`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.560s	595.040us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.490s	1.275ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	495.637us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.430s	11.804ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.500s	434.696us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.440s	539.476us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	495.637us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	434.696us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.230s	449.057us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.100s	376.049us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.593m	60.007ms	50	50	100.00
V2	jump	aon_timer_jump	1.550s	630.769us	50	50	100.00
V2	stress_all	aon_timer_stress_all	15.406m	623.194ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.260s	463.796us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.380s	840.473us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.380s	840.473us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.490s	1.275ms	5	5	100.00
		aon_timer_csr_rw	1.350s	495.637us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	434.696us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	2.571ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.490s	1.275ms	5	5	100.00
		aon_timer_csr_rw	1.350s	495.637us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	434.696us	5	5	100.00
		aon_timer_same_csr_outstanding	6.490s	2.571ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	3.890s	7.797ms	5	5	100.00
		aon_timer_tl_intg_err	13.190s	8.304ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.190s	8.304ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.969m	143.831ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.84	99.33	93.67	100.00	--	98.40	99.51	48.13

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 5 failures.

3.aon_timer_stress_all_with_rand_reset.32336137790546438056005771125631684149225256343962254555819506066236508160355
Line 349, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4869640528 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4869640528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.76283311403942008981468061383130360948920361714951447970104404847270020729909
Line 1247, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 679852338977 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 679852338977 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all has 4 failures.

5.aon_timer_stress_all.85183044293131166883393851702936208134917399278834451132379288988352011753211
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 46309725635 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 46309725635 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.aon_timer_stress_all.77464321703683528902128091241752968580707320704713374779304153257315245245751
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 56175867352 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 56175867352 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.