AON_TIMER Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	572.776us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.060s	1.214ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.470s	512.084us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	11.380s	7.294ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.420s	475.471us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.500s	575.890us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.470s	512.084us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	475.471us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.040s	329.214us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.390s	505.403us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.364m	51.234ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	610.861us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.355m	490.765ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.380s	518.915us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.910s	515.506us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.910s	515.506us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.060s	1.214ms	5	5	100.00
		aon_timer_csr_rw	1.470s	512.084us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	475.471us	5	5	100.00
		aon_timer_same_csr_outstanding	7.480s	2.777ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.060s	1.214ms	5	5	100.00
		aon_timer_csr_rw	1.470s	512.084us	20	20	100.00
		aon_timer_csr_aliasing	1.420s	475.471us	5	5	100.00
		aon_timer_same_csr_outstanding	7.480s	2.777ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	12.170s	7.297ms	5	5	100.00
		aon_timer_tl_intg_err	15.410s	8.916ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.410s	8.916ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.976m	985.072ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.42	99.33	93.67	100.00	--	98.40	99.51	51.60

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 12 failures:

Test aon_timer_stress_all has 3 failures.

4.aon_timer_stress_all.71228649535920392359191933946873881006624985514030725122512024874747961952282
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 50591805670 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 50591805670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.96407487832450228679867001212776172507473163571921754326778052459697798506722
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 7747468678 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7747468678 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 9 failures.

5.aon_timer_stress_all_with_rand_reset.56781653106705474422186029198267261317598039274901945577371686259664715942129
Line 473, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 10494800812 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 10494800812 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.aon_timer_stress_all_with_rand_reset.65463559625256551623262921223962566710568937083908445757960942119342979890413
Line 925, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 330907269832 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 330907269832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.