AON_TIMER Simulation Results

Saturday July 20 2024 23:02:34 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85433431889345478971181747401055702269263498582281270185582621732035232392187

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.460s	543.179us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.580s	1.307ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.200s	377.769us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	9.020s	13.300ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.320s	474.543us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.390s	495.491us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.200s	377.769us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	474.543us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.960s	315.653us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.040s	315.518us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.392m	53.480ms	50	50	100.00
V2	jump	aon_timer_jump	1.470s	571.188us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.447m	465.448ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.250s	488.494us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.640s	429.806us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.640s	429.806us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.580s	1.307ms	5	5	100.00
		aon_timer_csr_rw	1.200s	377.769us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	474.543us	5	5	100.00
		aon_timer_same_csr_outstanding	8.740s	2.895ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.580s	1.307ms	5	5	100.00
		aon_timer_csr_rw	1.200s	377.769us	20	20	100.00
		aon_timer_csr_aliasing	1.320s	474.543us	5	5	100.00
		aon_timer_same_csr_outstanding	8.740s	2.895ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	7.190s	4.540ms	5	5	100.00
		aon_timer_tl_intg_err	13.600s	7.901ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.600s	7.901ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.229m	469.158ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.01	99.33	93.67	100.00	--	98.40	99.51	49.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

5.aon_timer_stress_all_with_rand_reset.14943217760442230070949517195523113599434590949096305596952414708495740579517
Line 380, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4975770047 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4975770047 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all_with_rand_reset.64476681037516960060388574251599067586341709529243808863498048757020201634223
Line 351, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 30806025362 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30806025362 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 4 failures.

6.aon_timer_stress_all.70982127077297242887064360638194760391808780176539506398682596204621758689128
Line 265, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 30899242073 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30899242073 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all.98159460051531452625997184360272745010981830961296785253519362754164295190834
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 18065793576 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 18065793576 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.