AON_TIMER Simulation Results

Sunday July 21 2024 23:02:06 UTC

GitHub Revision: `e971cd9798`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 60538554475599760039478308558126864941531727393021608909386829062452482962039

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.500s	557.586us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.090s	996.817us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.250s	480.594us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	33.670s	13.748ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.600s	575.986us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	591.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.250s	480.594us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	575.986us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.840s	291.978us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.150s	486.929us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.375m	59.012ms	50	50	100.00
V2	jump	aon_timer_jump	1.520s	471.378us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.669m	441.464ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.280s	472.695us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.160s	622.689us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.160s	622.689us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.090s	996.817us	5	5	100.00
		aon_timer_csr_rw	1.250s	480.594us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	575.986us	5	5	100.00
		aon_timer_same_csr_outstanding	5.930s	2.355ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.090s	996.817us	5	5	100.00
		aon_timer_csr_rw	1.250s	480.594us	20	20	100.00
		aon_timer_csr_aliasing	1.600s	575.986us	5	5	100.00
		aon_timer_same_csr_outstanding	5.930s	2.355ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	7.720s	4.227ms	5	5	100.00
		aon_timer_tl_intg_err	14.350s	8.208ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.350s	8.208ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.995m	435.810ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.03	99.33	93.67	100.00	--	98.40	99.51	49.28

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

7.aon_timer_stress_all_with_rand_reset.60380909617928519303690320374505461601634093542945898989608469936984833550389
Line 940, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117912213579 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 117912213579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.aon_timer_stress_all_with_rand_reset.105419428951231457886213354742852677241390073777493043504897672266219899169817
Line 364, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 41209536181 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 41209536181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 1 failures.

26.aon_timer_stress_all.18573312608249555694132061405579243258319714610675033221101426129846475124271
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/26.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1733390263 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1733390263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---