AON_TIMER Simulation Results

Monday July 22 2024 23:02:17 UTC

GitHub Revision: `3e0219a2c5`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 78193674045195286552709223969981662100934453993551616519215297815848091296886

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	529.424us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.490s	1.242ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	480.770us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	22.770s	10.395ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.870s	625.782us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	569.058us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	480.770us	20	20	100.00
		aon_timer_csr_aliasing	1.870s	625.782us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.150s	440.604us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.230s	501.794us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.406m	53.049ms	50	50	100.00
V2	jump	aon_timer_jump	1.470s	587.699us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.967m	423.800ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.300s	517.540us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.190s	488.549us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.190s	488.549us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.490s	1.242ms	5	5	100.00
		aon_timer_csr_rw	1.410s	480.770us	20	20	100.00
		aon_timer_csr_aliasing	1.870s	625.782us	5	5	100.00
		aon_timer_same_csr_outstanding	4.750s	2.974ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.490s	1.242ms	5	5	100.00
		aon_timer_csr_rw	1.410s	480.770us	20	20	100.00
		aon_timer_csr_aliasing	1.870s	625.782us	5	5	100.00
		aon_timer_same_csr_outstanding	4.750s	2.974ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	5.940s	4.152ms	5	5	100.00
		aon_timer_tl_intg_err	14.300s	8.412ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.300s	8.412ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.370m	428.661ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			424	430	98.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.41	99.33	93.67	100.00	--	98.40	99.51	51.54

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

1.aon_timer_stress_all_with_rand_reset.1460620076956109678164981740725516190658112224358872248281902573414734351817
Line 411, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 8598653945 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 8598653945 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all_with_rand_reset.85479923346176914731619980109031374800642935138257450053678493366925676890374
Line 481, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 29386443203 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 29386443203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 3 failures.

8.aon_timer_stress_all.11299729532106644460443681736193021434323067705636146572252731801464672420024
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 54224379688 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 54224379688 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

28.aon_timer_stress_all.62295280198953700707845389898648228578008189135025087118366488190430854904116
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/28.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 931738185 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 931738185 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.