AON_TIMER Simulation Results

Tuesday July 23 2024 23:02:17 UTC

GitHub Revision: `0bfa990ddc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18885947517810151702135064218189465175127531856323617115052940021793720055953

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	522.695us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.430s	1.148ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	527.013us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.330s	7.091ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.470s	484.026us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	452.738us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	527.013us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	484.026us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.820s	432.574us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	502.138us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.642m	61.080ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	570.842us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.098m	293.166ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.230s	493.602us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.740s	473.252us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.740s	473.252us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.430s	1.148ms	5	5	100.00
		aon_timer_csr_rw	1.360s	527.013us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	484.026us	5	5	100.00
		aon_timer_same_csr_outstanding	8.470s	2.554ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.430s	1.148ms	5	5	100.00
		aon_timer_csr_rw	1.360s	527.013us	20	20	100.00
		aon_timer_csr_aliasing	1.470s	484.026us	5	5	100.00
		aon_timer_same_csr_outstanding	8.470s	2.554ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	8.770s	7.548ms	5	5	100.00
		aon_timer_tl_intg_err	14.700s	8.615ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.700s	8.615ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.648m	580.103ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.01	99.33	93.67	100.00	--	98.40	99.51	49.17

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 4 failures.

0.aon_timer_stress_all_with_rand_reset.99600625689910223817493442436295604366605392522657945271694665008020956554307
Line 342, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1558738472 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1558738472 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all_with_rand_reset.31490558496753036468487238581480163917959381807890955861642802297997047234411
Line 1258, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 60837825901 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 60837825901 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all has 1 failures.

14.aon_timer_stress_all.2590449087592222767480292212028987839811980356462770863062796588213177649055
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 125513367695 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 125513367695 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---