AON_TIMER Simulation Results

Wednesday July 24 2024 23:04:46 UTC

GitHub Revision: `e439226b6c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 80778109121175195808319778278610424989650974127729484509360263424111433728567

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	615.433us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.310s	1.142ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	504.308us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	12.270s	8.901ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.800s	530.047us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	466.783us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	504.308us	20	20	100.00
		aon_timer_csr_aliasing	1.800s	530.047us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.300s	509.273us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.320s	514.286us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.323m	51.244ms	50	50	100.00
V2	jump	aon_timer_jump	1.420s	559.269us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.449m	275.714ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.250s	463.840us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.620s	419.640us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.620s	419.640us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.310s	1.142ms	5	5	100.00
		aon_timer_csr_rw	1.350s	504.308us	20	20	100.00
		aon_timer_csr_aliasing	1.800s	530.047us	5	5	100.00
		aon_timer_same_csr_outstanding	4.950s	1.790ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.310s	1.142ms	5	5	100.00
		aon_timer_csr_rw	1.350s	504.308us	20	20	100.00
		aon_timer_csr_aliasing	1.800s	530.047us	5	5	100.00
		aon_timer_same_csr_outstanding	4.950s	1.790ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	6.280s	4.246ms	5	5	100.00
		aon_timer_tl_intg_err	13.410s	8.144ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.410s	8.144ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	22.280m	381.924ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.59	99.33	93.67	100.00	--	98.40	99.51	52.62

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

0.aon_timer_stress_all_with_rand_reset.15539085943671193930216433508211527038795308345900257669776331547958750539429
Line 830, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 75526339487 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 75526339487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.15789884786788437799610928238518935556364594776726346930617993427256811881961
Line 1179, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 290299251571 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 290299251571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 1 failures.

14.aon_timer_stress_all.70911221370793076170078840789653179396515641132956606769429150239011425250687
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 217818472808 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 217818472808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---