AON_TIMER Simulation Results

Thursday July 25 2024 23:02:35 UTC

GitHub Revision: `a47820eb4c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42717125255024305080795900498886328747526075712606813106869971419713539568742

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	574.053us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.570s	1.192ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.430s	524.064us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	16.600s	7.408ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.620s	556.608us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.420s	518.265us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.430s	524.064us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	556.608us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.730s	299.999us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.140s	457.767us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.520m	59.481ms	50	50	100.00
V2	jump	aon_timer_jump	1.430s	607.298us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.851m	576.956ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.340s	509.188us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.970s	436.938us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.970s	436.938us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.570s	1.192ms	5	5	100.00
		aon_timer_csr_rw	1.430s	524.064us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	556.608us	5	5	100.00
		aon_timer_same_csr_outstanding	6.870s	2.938ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.570s	1.192ms	5	5	100.00
		aon_timer_csr_rw	1.430s	524.064us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	556.608us	5	5	100.00
		aon_timer_same_csr_outstanding	6.870s	2.938ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	11.900s	8.473ms	5	5	100.00
		aon_timer_tl_intg_err	14.130s	8.632ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.130s	8.632ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.047m	531.084ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.54	99.33	93.67	100.00	--	98.40	99.51	52.33

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all_with_rand_reset has 8 failures.

0.aon_timer_stress_all_with_rand_reset.88151455082009638033672780918969347518899924094949441040571502082597822955200
Line 324, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7521639155 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7521639155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.aon_timer_stress_all_with_rand_reset.20129740425133899257132375903061850837012285948480392990701503881273604020018
Line 906, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 144083024922 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 144083024922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test aon_timer_stress_all has 2 failures.

7.aon_timer_stress_all.34125158984253599604263695275100008127199217537847352203485472423504403271039
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 37722234502 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 37722234502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aon_timer_stress_all.77285594651799657897339924720159258968853710566490714155522924453121372898237
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 44253357057 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 44253357057 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---