AON_TIMER Simulation Results

Friday July 26 2024 23:02:17 UTC

GitHub Revision: `4877b481e8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 32772136499307530671572864311472020383177374948143841887013058662761887638244

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.420s	563.896us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.530s	675.397us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	501.840us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	21.140s	14.034ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.610s	522.819us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.580s	549.078us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	501.840us	20	20	100.00
		aon_timer_csr_aliasing	1.610s	522.819us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.050s	348.225us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.230s	502.340us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.097m	47.763ms	50	50	100.00
V2	jump	aon_timer_jump	1.440s	548.547us	50	50	100.00
V2	stress_all	aon_timer_stress_all	12.010m	451.665ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.370s	513.298us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.980s	485.639us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.980s	485.639us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.530s	675.397us	5	5	100.00
		aon_timer_csr_rw	1.380s	501.840us	20	20	100.00
		aon_timer_csr_aliasing	1.610s	522.819us	5	5	100.00
		aon_timer_same_csr_outstanding	4.850s	2.411ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.530s	675.397us	5	5	100.00
		aon_timer_csr_rw	1.380s	501.840us	20	20	100.00
		aon_timer_csr_aliasing	1.610s	522.819us	5	5	100.00
		aon_timer_same_csr_outstanding	4.850s	2.411ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	12.030s	8.576ms	5	5	100.00
		aon_timer_tl_intg_err	12.260s	7.677ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.260s	7.677ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	14.969m	80.582ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.79	99.33	93.67	100.00	--	98.40	99.51	47.82

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all has 3 failures.

9.aon_timer_stress_all.96293239636744941443129065848687565787825186076332589592517971872667272679246
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 41911882502 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 41911882502 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.aon_timer_stress_all.79343100082458983743084047821362256888711593274109372805414910474880705916546
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/33.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 100415886499 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 100415886499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 6 failures.

15.aon_timer_stress_all_with_rand_reset.94636800699569295865416934037565878074321705337848772764305323802370189835027
Line 267, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 845258360 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 845258360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

34.aon_timer_stress_all_with_rand_reset.10828884887675820918418885351126839680599609118252494740555872554372958007240
Line 255, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/34.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 732303262 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 732303262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.