AON_TIMER Simulation Results

Saturday July 27 2024 23:02:25 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6528518538521148567139195500524222710943459299328477504124649113671643189924

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.380s	596.205us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.430s	1.179ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	533.077us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	12.850s	8.771ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.410s	435.332us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	548.164us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	533.077us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	435.332us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.100s	414.386us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.310s	519.734us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.463m	60.378ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	542.903us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.280m	515.936ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.310s	482.992us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.230s	437.066us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.230s	437.066us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.430s	1.179ms	5	5	100.00
		aon_timer_csr_rw	1.380s	533.077us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	435.332us	5	5	100.00
		aon_timer_same_csr_outstanding	5.790s	1.700ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.430s	1.179ms	5	5	100.00
		aon_timer_csr_rw	1.380s	533.077us	20	20	100.00
		aon_timer_csr_aliasing	1.410s	435.332us	5	5	100.00
		aon_timer_same_csr_outstanding	5.790s	1.700ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	13.360s	8.336ms	5	5	100.00
		aon_timer_tl_intg_err	14.540s	8.566ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.540s	8.566ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.670m	181.370ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.06	99.33	93.67	100.00	--	98.40	99.51	49.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all has 2 failures.

6.aon_timer_stress_all.112057679026191490680042396951184141097701940432828853849904709660142515901575
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1679215556 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1679215556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.3384148387292411312751916738166297061901268352971348335793177851627221430965
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 130598580863 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 130598580863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 5 failures.

24.aon_timer_stress_all_with_rand_reset.43214220859981839600196031039512180895403996283065299803924799124205966665427
Line 259, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 734940588 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 734940588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aon_timer_stress_all_with_rand_reset.76650181809676683355399665451988534294776460497935998583242826025149352755843
Line 813, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/30.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 107582933783 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 107582933783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.