AON_TIMER Simulation Results

Sunday July 28 2024 23:02:28 UTC

GitHub Revision: `eca25c0ff8`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 35694793988142953409419697382868702825984401131209466119932029294128690866559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.430s	540.651us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.270s	1.106ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.280s	522.011us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	9.230s	11.614ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.480s	632.066us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	541.202us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.280s	522.011us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	632.066us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	426.945us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.330s	505.999us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.109m	60.939ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	592.423us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.974m	533.115ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.270s	483.430us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.490s	763.544us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.490s	763.544us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.270s	1.106ms	5	5	100.00
		aon_timer_csr_rw	1.280s	522.011us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	632.066us	5	5	100.00
		aon_timer_same_csr_outstanding	7.860s	2.349ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.270s	1.106ms	5	5	100.00
		aon_timer_csr_rw	1.280s	522.011us	20	20	100.00
		aon_timer_csr_aliasing	1.480s	632.066us	5	5	100.00
		aon_timer_same_csr_outstanding	7.860s	2.349ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	6.120s	4.083ms	5	5	100.00
		aon_timer_tl_intg_err	12.980s	7.951ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.980s	7.951ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	11.816m	64.824ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.93	99.33	93.67	100.00	--	98.40	99.51	48.66

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:470) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

4.aon_timer_stress_all_with_rand_reset.1841479906460492597968066043475601643880926192819126520937824385387616580753
Line 291, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1075217070 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1075217070 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.84815922302973452356857730360697236225545602526517875886930337614499049843276
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1525016149 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1525016149 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 2 failures.

7.aon_timer_stress_all.1814497393493425965616332674619967247619441915919047286804459650948361145917
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 93100764028 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 93100764028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

44.aon_timer_stress_all.71858772101966656343044940163602577863635436465570243570697111354050739097676
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/44.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1465137327 ps: (cip_base_vseq.sv:470) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1465137327 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---