39f3866b56| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.440s | 542.307us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.100s | 928.091us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.340s | 539.427us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 17.860s | 6.953ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.600s | 563.763us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.580s | 559.227us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.340s | 539.427us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.600s | 563.763us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.160s | 517.008us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.170s | 470.763us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.459m | 61.503ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.460s | 550.905us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 12.902m | 484.811ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.280s | 514.748us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.070s | 612.836us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.070s | 612.836us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.100s | 928.091us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.340s | 539.427us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.600s | 563.763us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.910s | 2.595ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.100s | 928.091us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.340s | 539.427us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.600s | 563.763us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.910s | 2.595ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 13.240s | 8.126ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 12.810s | 8.364ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 12.810s | 8.364ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 16.973m | 95.254ms | 43 | 50 | 86.00 |
| V3 | TOTAL | 43 | 50 | 86.00 | |||
| TOTAL | 423 | 430 | 98.37 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.86 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 48.29 |
UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 7 failures:
14.aon_timer_stress_all_with_rand_reset.74443397138354248685764339360959659866972218197287957835837833933349785072636
Line 296, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1502610046 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1502610046 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
19.aon_timer_stress_all_with_rand_reset.103037347827178509586114776293080998565520565767611978727821164923614062428397
Line 886, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 39717353400 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 39717353400 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.