AON_TIMER Simulation Results

Tuesday July 30 2024 23:02:08 UTC

GitHub Revision: `fdfa12db04`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 101467584611478134588291649782725219255540557286164709436567235390830780957271

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.460s	595.086us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.060s	1.133ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.440s	535.047us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	14.740s	7.275ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.810s	749.195us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.520s	519.408us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.440s	535.047us	20	20	100.00
		aon_timer_csr_aliasing	1.810s	749.195us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.930s	272.276us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.230s	487.820us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.287m	54.812ms	50	50	100.00
V2	jump	aon_timer_jump	1.410s	437.880us	50	50	100.00
V2	stress_all	aon_timer_stress_all	16.569m	669.666ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.320s	448.542us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.790s	567.705us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.790s	567.705us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.060s	1.133ms	5	5	100.00
		aon_timer_csr_rw	1.440s	535.047us	20	20	100.00
		aon_timer_csr_aliasing	1.810s	749.195us	5	5	100.00
		aon_timer_same_csr_outstanding	4.710s	1.678ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.060s	1.133ms	5	5	100.00
		aon_timer_csr_rw	1.440s	535.047us	20	20	100.00
		aon_timer_csr_aliasing	1.810s	749.195us	5	5	100.00
		aon_timer_same_csr_outstanding	4.710s	1.678ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	3.860s	4.249ms	5	5	100.00
		aon_timer_tl_intg_err	14.480s	8.817ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.480s	8.817ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	20.539m	449.471ms	39	50	78.00
V3		TOTAL			39	50	78.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.17	99.33	93.67	100.00	--	98.40	99.51	50.10

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 11 failures.

1.aon_timer_stress_all_with_rand_reset.72207594125704638554858383675517419035857012184275369156390378987027618028584
Line 279, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 883583371 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 883583371 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.104934381597081249041702726874481213814220025541097881756088678934957647446618
Line 494, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 14514833629 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14514833629 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test aon_timer_stress_all has 2 failures.

3.aon_timer_stress_all.97969955655082034582522322116042663042450284257867251086964527836882958875290
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 89655267933 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 89655267933 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all.100818251057996574870467308431635308871428191116704962163718990824824671906812
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 370999529 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 370999529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---