AON_TIMER Simulation Results

Wednesday July 31 2024 23:02:38 UTC

GitHub Revision: `e9b7e615a7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 25204348267605859133056659113100703417171299070132656462514712657132693373848

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.370s	498.179us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	0.990s	1.263ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.380s	502.552us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	5.160s	8.292ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.500s	612.289us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.390s	467.412us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.380s	502.552us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	612.289us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.210s	426.120us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.240s	454.678us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.433m	59.896ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	577.368us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.170m	539.502ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.310s	496.336us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.530s	1.142ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.530s	1.142ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	0.990s	1.263ms	5	5	100.00
		aon_timer_csr_rw	1.380s	502.552us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	612.289us	5	5	100.00
		aon_timer_same_csr_outstanding	8.350s	3.161ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	0.990s	1.263ms	5	5	100.00
		aon_timer_csr_rw	1.380s	502.552us	20	20	100.00
		aon_timer_csr_aliasing	1.500s	612.289us	5	5	100.00
		aon_timer_same_csr_outstanding	8.350s	3.161ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	5.710s	4.019ms	5	5	100.00
		aon_timer_tl_intg_err	14.780s	8.368ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.780s	8.368ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	13.942m	157.632ms	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			416	430	96.74

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.81	99.33	93.67	100.00	--	98.40	99.51	47.93

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 14 failures:

Test aon_timer_stress_all_with_rand_reset has 13 failures.

2.aon_timer_stress_all_with_rand_reset.102074276548572503208557231335858481555590821038913819597326712759132468391735
Line 337, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2932812432 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2932812432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.aon_timer_stress_all_with_rand_reset.8293569394244538213271881844013433308253896381047871638600161390495365655663
Line 1176, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 266381823958 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 266381823958 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test aon_timer_stress_all has 1 failures.

21.aon_timer_stress_all.62550871655171653119294014824035687575850614717880455127150372737319955368657
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 56332497250 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 56332497250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---