AON_TIMER Simulation Results

Thursday August 01 2024 23:02:20 UTC

GitHub Revision: `625f353e9c`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 85273092133191575795496895645039765542965103003083525273509664765586668778052

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	587.369us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.220s	1.160ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	534.840us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	28.630s	8.750ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.790s	481.541us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.350s	496.727us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	534.840us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	481.541us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	508.112us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.060s	390.530us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.479m	57.440ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	591.562us	50	50	100.00
V2	stress_all	aon_timer_stress_all	13.765m	524.513ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	1.260s	481.374us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.890s	1.028ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.890s	1.028ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.220s	1.160ms	5	5	100.00
		aon_timer_csr_rw	1.350s	534.840us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	481.541us	5	5	100.00
		aon_timer_same_csr_outstanding	8.740s	2.883ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.220s	1.160ms	5	5	100.00
		aon_timer_csr_rw	1.350s	534.840us	20	20	100.00
		aon_timer_csr_aliasing	1.790s	481.541us	5	5	100.00
		aon_timer_same_csr_outstanding	8.740s	2.883ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	13.190s	8.443ms	5	5	100.00
		aon_timer_tl_intg_err	13.480s	8.841ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.480s	8.841ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	14.692m	429.895ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.66	99.33	93.67	100.00	--	98.40	99.51	47.07

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all has 3 failures.

3.aon_timer_stress_all.92833416101486003089794030095545419975496797227072043546807487936039910561976
Line 281, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2188929582 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2188929582 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.39670676550178798283905111870381610572787857612813769943015764624145520895256
Line 273, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 22619627542 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 22619627542 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 5 failures.

11.aon_timer_stress_all_with_rand_reset.8955897609748368026747212591031007849144088569612977508719051589185314488370
Line 899, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23625959788 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 23625959788 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.23084147604640418882277682588403703961709642402796364597980363651645298782012
Line 848, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 33764104545 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 33764104545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.