c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.340s | 589.845us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.330s | 1.099ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.350s | 517.699us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 27.840s | 7.575ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.770s | 582.356us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.480s | 458.243us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.350s | 517.699us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.770s | 582.356us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.220s | 481.885us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.120s | 490.138us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.265m | 49.906ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.450s | 576.375us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 10.707m | 463.937ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.260s | 506.980us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.900s | 515.138us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.900s | 515.138us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.330s | 1.099ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.350s | 517.699us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.770s | 582.356us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.820s | 2.203ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.330s | 1.099ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.350s | 517.699us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.770s | 582.356us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.820s | 2.203ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 6.970s | 8.146ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 15.250s | 9.197ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 15.250s | 9.197ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 25.650m | 556.917ms | 47 | 50 | 94.00 |
| V3 | TOTAL | 47 | 50 | 94.00 | |||
| TOTAL | 427 | 430 | 99.30 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.92 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 48.64 |
UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 3 failures:
9.aon_timer_stress_all_with_rand_reset.74548731939500689027810746610367837491964730044406659359215008301464535798899
Line 1682, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 105523046241 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 105523046241 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
16.aon_timer_stress_all_with_rand_reset.59903944117481629347982069988362285922527708172808839944845212625120412222768
Line 277, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/16.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1850959886 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1850959886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.