c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.430s | 554.932us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.030s | 1.106ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.300s | 426.634us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 36.490s | 12.783ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.390s | 522.293us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.450s | 463.077us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.300s | 426.634us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.390s | 522.293us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.810s | 358.884us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.070s | 442.066us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.544m | 59.934ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.410s | 550.193us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 11.387m | 427.853ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.300s | 499.763us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.320s | 530.279us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.320s | 530.279us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.030s | 1.106ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.300s | 426.634us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.390s | 522.293us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.020s | 2.106ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.030s | 1.106ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.300s | 426.634us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.390s | 522.293us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 7.020s | 2.106ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 6.920s | 4.130ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 14.700s | 8.619ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 14.700s | 8.619ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 18.420m | 99.956ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 425 | 430 | 98.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 90.38 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 51.36 |
UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 5 failures:
9.aon_timer_stress_all_with_rand_reset.68887419160929378685254724064938335836470972068430738640636167340422667390627
Line 649, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 197024306667 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 197024306667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
22.aon_timer_stress_all_with_rand_reset.112804007964591422524094739351639374550535065650396886385506231825196907382720
Line 697, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 79933978248 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 79933978248 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.