AON_TIMER Simulation Results

Sunday August 04 2024 23:02:21 UTC

GitHub Revision: c8985d6745

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107130591329296133632864610148388701578652631018704528920799220771546870921898

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke aon_timer_smoke 1.480s 605.843us 50 50 100.00
V1 csr_hw_reset aon_timer_csr_hw_reset 1.780s 724.660us 5 5 100.00
V1 csr_rw aon_timer_csr_rw 1.380s 532.094us 20 20 100.00
V1 csr_bit_bash aon_timer_csr_bit_bash 16.560s 12.337ms 5 5 100.00
V1 csr_aliasing aon_timer_csr_aliasing 1.610s 575.397us 5 5 100.00
V1 csr_mem_rw_with_rand_reset aon_timer_csr_mem_rw_with_rand_reset 1.580s 549.338us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr aon_timer_csr_rw 1.380s 532.094us 20 20 100.00
aon_timer_csr_aliasing 1.610s 575.397us 5 5 100.00
V1 mem_walk aon_timer_mem_walk 1.180s 428.993us 5 5 100.00
V1 mem_partial_access aon_timer_mem_partial_access 1.010s 347.398us 5 5 100.00
V1 TOTAL 115 115 100.00
V2 prescaler aon_timer_prescaler 1.202m 53.014ms 50 50 100.00
V2 jump aon_timer_jump 1.500s 565.785us 50 50 100.00
V2 stress_all aon_timer_stress_all 10.492m 474.385ms 49 50 98.00
V2 intr_test aon_timer_intr_test 1.260s 487.566us 50 50 100.00
V2 tl_d_oob_addr_access aon_timer_tl_errors 2.980s 379.204us 20 20 100.00
V2 tl_d_illegal_access aon_timer_tl_errors 2.980s 379.204us 20 20 100.00
V2 tl_d_outstanding_access aon_timer_csr_hw_reset 1.780s 724.660us 5 5 100.00
aon_timer_csr_rw 1.380s 532.094us 20 20 100.00
aon_timer_csr_aliasing 1.610s 575.397us 5 5 100.00
aon_timer_same_csr_outstanding 7.580s 2.840ms 20 20 100.00
V2 tl_d_partial_access aon_timer_csr_hw_reset 1.780s 724.660us 5 5 100.00
aon_timer_csr_rw 1.380s 532.094us 20 20 100.00
aon_timer_csr_aliasing 1.610s 575.397us 5 5 100.00
aon_timer_same_csr_outstanding 7.580s 2.840ms 20 20 100.00
V2 TOTAL 239 240 99.58
V2S tl_intg_err aon_timer_sec_cm 13.630s 8.496ms 5 5 100.00
aon_timer_tl_intg_err 14.280s 8.659ms 20 20 100.00
V2S sec_cm_bus_integrity aon_timer_tl_intg_err 14.280s 8.659ms 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset aon_timer_stress_all_with_rand_reset 14.177m 103.607ms 44 50 88.00
V3 TOTAL 44 50 88.00
TOTAL 423 430 98.37

Testplan Progress

Items Total Written Passing Progress
V1 8 8 8 100.00
V2 6 6 5 83.33
V2S 2 2 2 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
90.06 99.33 93.67 100.00 -- 98.40 99.51 49.48

Failure Buckets

Past Results