e4c5daa580| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.480s | 592.877us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.960s | 1.185ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.450s | 535.316us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 19.870s | 14.311ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.420s | 548.257us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.510s | 511.884us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.450s | 535.316us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.420s | 548.257us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 0.970s | 319.822us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 1.110s | 425.943us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.320m | 56.992ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.510s | 586.871us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 12.891m | 542.200ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.400s | 512.466us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.190s | 513.792us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.190s | 513.792us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.960s | 1.185ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.450s | 535.316us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.420s | 548.257us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.010s | 1.405ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.960s | 1.185ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.450s | 535.316us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.420s | 548.257us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 4.010s | 1.405ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 12.950s | 7.611ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 12.770s | 8.185ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 12.770s | 8.185ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 15.343m | 84.736ms | 44 | 50 | 88.00 |
| V3 | TOTAL | 44 | 50 | 88.00 | |||
| TOTAL | 424 | 430 | 98.60 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.93 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 48.66 |
UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:
0.aon_timer_stress_all_with_rand_reset.19822578822451729137384635057129095545445609028902035898141082944439925824276
Line 606, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 22108229190 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 22108229190 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.aon_timer_stress_all_with_rand_reset.52096980940438639895036177668347903253071943091620032313651250852246837647805
Line 286, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/7.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1180521987 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1180521987 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.