AON_TIMER Simulation Results

Tuesday August 06 2024 23:02:29 UTC

GitHub Revision: `5fd4ecc0fc`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56304622830272859824235340993951659280265419461975949533183046575604373639200

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.500s	605.842us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.680s	799.351us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.360s	554.780us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.080s	13.805ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.760s	522.090us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	561.214us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.360s	554.780us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	522.090us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.800s	285.676us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.250s	467.397us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	59.740s	41.316ms	50	50	100.00
V2	jump	aon_timer_jump	1.490s	574.929us	50	50	100.00
V2	stress_all	aon_timer_stress_all	24.286m	975.642ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.310s	507.608us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.840s	394.260us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.840s	394.260us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.680s	799.351us	5	5	100.00
		aon_timer_csr_rw	1.360s	554.780us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	522.090us	5	5	100.00
		aon_timer_same_csr_outstanding	7.990s	2.295ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.680s	799.351us	5	5	100.00
		aon_timer_csr_rw	1.360s	554.780us	20	20	100.00
		aon_timer_csr_aliasing	1.760s	522.090us	5	5	100.00
		aon_timer_same_csr_outstanding	7.990s	2.295ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	6.150s	8.074ms	5	5	100.00
		aon_timer_tl_intg_err	14.590s	9.062ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.590s	9.062ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	15.848m	108.333ms	42	50	84.00
V3		TOTAL			42	50	84.00
		TOTAL			418	430	97.21

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.13	99.33	93.67	100.00	--	98.40	99.51	49.86

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all_with_rand_reset has 7 failures.

3.aon_timer_stress_all_with_rand_reset.102383247838877914154447395674957678635582339304617304750717617397395672876909
Line 504, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 23656503828 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 23656503828 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all_with_rand_reset.106428075813227386385328456730020848645085390663111927939170472456937988764472
Line 1129, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 70736745886 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 70736745886 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test aon_timer_stress_all has 4 failures.

8.aon_timer_stress_all.73326163502022173811439059156212271171300940422418206343389393713778917954021
Line 285, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/8.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 38061797973 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 38061797973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.aon_timer_stress_all.42123876332443271630580692093481571422605252045518891786336519606106277724670
Line 257, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1072182721 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1072182721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:304) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 5.aon_timer_stress_all_with_rand_reset.72576754998595510994668285107609613450155560374070942125886315965726126927654
    Line 360, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 44153605536 ps: (aon_timer_scoreboard.sv:304) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 44153605536 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```