AON_TIMER Simulation Results

Wednesday August 07 2024 23:02:33 UTC

GitHub Revision: `bbf435ceff`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6888687353677204195542416712589698377810102273194685652880785004967849651007

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.460s	617.068us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.270s	1.093ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	538.836us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	31.390s	11.677ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.460s	569.456us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	830.967us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	538.836us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	569.456us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.220s	437.372us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.750s	281.819us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.236m	50.980ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	583.567us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.584m	634.375ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.320s	518.077us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.330s	593.065us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.330s	593.065us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.270s	1.093ms	5	5	100.00
		aon_timer_csr_rw	1.410s	538.836us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	569.456us	5	5	100.00
		aon_timer_same_csr_outstanding	5.480s	2.381ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.270s	1.093ms	5	5	100.00
		aon_timer_csr_rw	1.410s	538.836us	20	20	100.00
		aon_timer_csr_aliasing	1.460s	569.456us	5	5	100.00
		aon_timer_same_csr_outstanding	5.480s	2.381ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	11.130s	8.489ms	5	5	100.00
		aon_timer_tl_intg_err	14.790s	8.131ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.790s	8.131ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	21.390m	126.512ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.81	99.33	93.67	100.00	--	98.40	99.51	47.98

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all has 4 failures.

3.aon_timer_stress_all.97570991227169494660758774502343128154516608121060865193610665232999157145950
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 613564756 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 613564756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all.99727116196371030406948765724077828653439110921516202052497123680996053599699
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 22753248833 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 22753248833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 4 failures.

15.aon_timer_stress_all_with_rand_reset.24482053254235003119011166959332569064045971093832852859678912721840699076425
Line 260, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 738111493 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 738111493 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.aon_timer_stress_all_with_rand_reset.24852065395042967671466014396494469621003799699621473629337507382589422074287
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 796528563 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 796528563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.