AON_TIMER Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: `3707c48f56`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.480s	563.017us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.880s	950.486us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.400s	531.905us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	34.140s	13.876ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.980s	567.924us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.470s	530.695us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.400s	531.905us	20	20	100.00
		aon_timer_csr_aliasing	1.980s	567.924us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.190s	465.743us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.350s	460.996us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.381m	52.862ms	50	50	100.00
V2	jump	aon_timer_jump	1.530s	539.860us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.579m	432.837ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.290s	508.398us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.370s	605.096us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.370s	605.096us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.880s	950.486us	5	5	100.00
		aon_timer_csr_rw	1.400s	531.905us	20	20	100.00
		aon_timer_csr_aliasing	1.980s	567.924us	5	5	100.00
		aon_timer_same_csr_outstanding	7.920s	2.769ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.880s	950.486us	5	5	100.00
		aon_timer_csr_rw	1.400s	531.905us	20	20	100.00
		aon_timer_csr_aliasing	1.980s	567.924us	5	5	100.00
		aon_timer_same_csr_outstanding	7.920s	2.769ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	10.380s	7.204ms	5	5	100.00
		aon_timer_tl_intg_err	14.180s	8.419ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.180s	8.419ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	19.343m	587.020ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.53	99.33	93.67	100.00	--	98.40	99.51	52.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

3.aon_timer_stress_all_with_rand_reset.49930109589393363996760619981998494263498426507558423769138458861921224590194
Line 488, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 15289284432 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 15289284432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.aon_timer_stress_all_with_rand_reset.4825235395274315159938461437753216053243209609823301247067508349882096175527
Line 369, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/5.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4024318813 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4024318813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 1 failures.

48.aon_timer_stress_all.21429837179187591825991931256171607676096058452062895079878361090283070135814
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 46100265568 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 46100265568 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---