AON_TIMER Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.520s	552.228us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.490s	1.172ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.330s	479.881us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	26.340s	11.571ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.680s	678.293us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.510s	562.602us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.330s	479.881us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	678.293us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	465.127us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.250s	479.019us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.441m	59.373ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	571.862us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.675m	429.821ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.270s	510.658us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.860s	526.846us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.860s	526.846us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.490s	1.172ms	5	5	100.00
		aon_timer_csr_rw	1.330s	479.881us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	678.293us	5	5	100.00
		aon_timer_same_csr_outstanding	5.500s	2.475ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.490s	1.172ms	5	5	100.00
		aon_timer_csr_rw	1.330s	479.881us	20	20	100.00
		aon_timer_csr_aliasing	1.680s	678.293us	5	5	100.00
		aon_timer_same_csr_outstanding	5.500s	2.475ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	11.430s	8.197ms	5	5	100.00
		aon_timer_tl_intg_err	13.900s	8.549ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.900s	8.549ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	23.510m	125.254ms	38	50	76.00
V3		TOTAL			38	50	76.00
		TOTAL			417	430	96.98

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.23	99.33	93.67	100.00	--	98.40	99.51	50.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 13 failures:

Test aon_timer_stress_all_with_rand_reset has 12 failures.

4.aon_timer_stress_all_with_rand_reset.68000625359455220832850907535987669396660729286252726926577576319430821093760
Line 269, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/4.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1457882749 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1457882749 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.aon_timer_stress_all_with_rand_reset.83636434433960119369810766182747875448811557709376581844395579222755676424555
Line 295, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1513004219 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1513004219 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test aon_timer_stress_all has 1 failures.

39.aon_timer_stress_all.39125077856109373853912901812578511686457584413914421728225484344115859748818
Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/39.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 99497089774 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 99497089774 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---