AON_TIMER Simulation Results

Saturday August 10 2024 23:02:23 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 2196818177928134427831197337249851347498377272679561983541244979366753055772

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.560s	566.545us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.550s	1.296ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.430s	533.439us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	27.490s	13.493ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.400s	524.571us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.410s	471.008us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.430s	533.439us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	524.571us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.160s	480.610us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.190s	500.711us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.463m	59.139ms	50	50	100.00
V2	jump	aon_timer_jump	1.360s	524.300us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.213m	246.095ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.380s	440.101us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.000s	747.554us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.000s	747.554us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.550s	1.296ms	5	5	100.00
		aon_timer_csr_rw	1.430s	533.439us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	524.571us	5	5	100.00
		aon_timer_same_csr_outstanding	5.030s	1.426ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.550s	1.296ms	5	5	100.00
		aon_timer_csr_rw	1.430s	533.439us	20	20	100.00
		aon_timer_csr_aliasing	1.400s	524.571us	5	5	100.00
		aon_timer_same_csr_outstanding	5.030s	1.426ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	12.430s	8.037ms	5	5	100.00
		aon_timer_tl_intg_err	15.200s	8.907ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.200s	8.907ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	16.164m	131.327ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			422	430	98.14

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.78	99.33	93.67	100.00	--	98.40	99.51	47.76

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

15.aon_timer_stress_all_with_rand_reset.3565635925674224011722890275606769766917616537996325875220870839588687971803
Line 1561, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 285447230181 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 285447230181 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.15294472286178650490958445493672576172295131067449793274891359385048530297110
Line 616, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 67317261686 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 67317261686 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 2 failures.

40.aon_timer_stress_all.10630086774684907271458830315157869585362977614970350652188315997053750950837
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/40.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 246095481689 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 246095481689 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

41.aon_timer_stress_all.101283139227586698390127747818774174628125597195956330403765663324566536048965
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/41.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 99756994719 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 99756994719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---