AON_TIMER Simulation Results

Sunday August 11 2024 23:02:21 UTC

GitHub Revision: `07b417ef03`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 6142445146730822936893044599112392910298048088673599708943858624824800218011

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.530s	606.589us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.590s	1.357ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.410s	532.745us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	18.490s	13.684ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.670s	495.625us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.550s	557.904us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.410s	532.745us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	495.625us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.940s	326.663us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.140s	434.792us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.258m	53.122ms	50	50	100.00
V2	jump	aon_timer_jump	1.450s	571.562us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.769m	417.969ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.300s	493.520us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.240s	535.034us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.240s	535.034us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.590s	1.357ms	5	5	100.00
		aon_timer_csr_rw	1.410s	532.745us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	495.625us	5	5	100.00
		aon_timer_same_csr_outstanding	6.280s	2.850ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.590s	1.357ms	5	5	100.00
		aon_timer_csr_rw	1.410s	532.745us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	495.625us	5	5	100.00
		aon_timer_same_csr_outstanding	6.280s	2.850ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	11.980s	8.194ms	5	5	100.00
		aon_timer_tl_intg_err	14.230s	8.243ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.230s	8.243ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	17.778m	112.730ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.09	99.33	93.67	100.00	--	98.40	99.51	49.61

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:467) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 5 failures.

9.aon_timer_stress_all_with_rand_reset.67237446899076778012181722731669267549949254759396844833727629170365684825175
Line 1238, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/9.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 561200483274 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 561200483274 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.aon_timer_stress_all_with_rand_reset.11539018294810707100518452662109763209721920952622548156863982930464902621522
Line 430, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 20920434736 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 20920434736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all has 1 failures.

27.aon_timer_stress_all.61726441719982440548628722129211265104249655334892428978806944090202363384709
Line 261, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 30401197407 ps: (cip_base_vseq.sv:467) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 30401197407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:755) [aon_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 3.aon_timer_stress_all_with_rand_reset.52048042930695322585959464564721156309682251628655404568827427650291921837338
    Line 252, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 505470783 ps: (cip_base_vseq.sv:755) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 505470783 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```