AON_TIMER Simulation Results

Monday August 12 2024 23:02:30 UTC

GitHub Revision: `c082b8981f`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107262934208806092150901079363789224644653433402469901409990667510497383888850

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.450s	572.249us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.370s	1.228ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.350s	483.437us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	24.360s	10.115ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.510s	468.703us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.560s	529.116us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.350s	483.437us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	468.703us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.250s	508.485us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.260s	461.618us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.452m	55.917ms	50	50	100.00
V2	jump	aon_timer_jump	1.480s	594.618us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.238m	405.794ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.350s	496.925us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.450s	538.965us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.450s	538.965us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.370s	1.228ms	5	5	100.00
		aon_timer_csr_rw	1.350s	483.437us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	468.703us	5	5	100.00
		aon_timer_same_csr_outstanding	5.980s	2.144ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.370s	1.228ms	5	5	100.00
		aon_timer_csr_rw	1.350s	483.437us	20	20	100.00
		aon_timer_csr_aliasing	1.510s	468.703us	5	5	100.00
		aon_timer_same_csr_outstanding	5.980s	2.144ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.100s	7.801ms	5	5	100.00
		aon_timer_tl_intg_err	14.610s	8.295ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.610s	8.295ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.062m	33.150ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.69	99.33	93.67	100.00	--	98.40	99.51	47.25

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all_with_rand_reset has 3 failures.

6.aon_timer_stress_all_with_rand_reset.22456115869461531057481796137195907041216051115109971243954139349938095488722
Line 502, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6299857067 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6299857067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

48.aon_timer_stress_all_with_rand_reset.64549262935894325716306991304633277625227507932011853536801888211154478954775
Line 290, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/48.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1185661846 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1185661846 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all has 1 failures.

43.aon_timer_stress_all.76894768246937207946878469742964429480297953697916397112436947632855621720650
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/43.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 48634136466 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 48634136466 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---