098010d125| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 1.430s | 565.058us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.420s | 1.219ms | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 1.260s | 507.246us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 27.730s | 13.899ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 1.790s | 595.331us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 1.370s | 457.192us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 1.260s | 507.246us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 1.790s | 595.331us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.120s | 431.210us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 0.970s | 348.723us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 1.345m | 54.547ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 1.500s | 616.776us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 8.014m | 389.483ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 1.320s | 466.916us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 2.510s | 676.619us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 2.510s | 676.619us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.420s | 1.219ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.260s | 507.246us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.790s | 595.331us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 6.690s | 2.630ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.420s | 1.219ms | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 1.260s | 507.246us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 1.790s | 595.331us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 6.690s | 2.630ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 11.250s | 7.981ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 15.060s | 8.482ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 15.060s | 8.482ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 52.040s | 25.805ms | 46 | 50 | 92.00 |
| V3 | TOTAL | 46 | 50 | 92.00 | |||
| TOTAL | 426 | 430 | 99.07 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.04 | 99.33 | 93.67 | 100.00 | -- | 98.40 | 99.51 | 43.34 |
UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 4 failures:
19.aon_timer_stress_all_with_rand_reset.33906533170712462857210821073148090209172417313759313611078258255958268670113
Line 418, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/19.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 2274274903 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 2274274903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
23.aon_timer_stress_all_with_rand_reset.66848039632910054852587214611048154144820850222984260140162005970242358033726
Line 465, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/23.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 53615482363 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 53615482363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.