AON_TIMER Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: `584c3d46af`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.380s	563.837us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.030s	898.545us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.230s	394.187us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	6.640s	11.783ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.670s	592.207us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.500s	561.453us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.230s	394.187us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	592.207us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.270s	503.401us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.170s	430.267us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.282m	56.951ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	565.154us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.938m	452.941ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.490s	495.005us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.660s	498.355us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.660s	498.355us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.030s	898.545us	5	5	100.00
		aon_timer_csr_rw	1.230s	394.187us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	592.207us	5	5	100.00
		aon_timer_same_csr_outstanding	5.160s	2.391ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.030s	898.545us	5	5	100.00
		aon_timer_csr_rw	1.230s	394.187us	20	20	100.00
		aon_timer_csr_aliasing	1.670s	592.207us	5	5	100.00
		aon_timer_same_csr_outstanding	5.160s	2.391ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	11.580s	7.502ms	5	5	100.00
		aon_timer_tl_intg_err	14.770s	8.460ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.770s	8.460ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.094m	22.714ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.05	99.33	93.67	100.00	--	98.40	99.51	43.43

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 8 failures:

Test aon_timer_stress_all has 4 failures.

0.aon_timer_stress_all.53295095862832159020122065633137979822189494987102496809117549256111147303033
Line 333, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/0.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 5136264573 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 5136264573 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.aon_timer_stress_all.18017507008996527215618684756267867222934833420188334185241182294006009367873
Line 289, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/2.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 160299801832 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 160299801832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 4 failures.

21.aon_timer_stress_all_with_rand_reset.14409547349074364936362030064512792305462843792541458035698061841589197373853
Line 435, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3154752798 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3154752798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.aon_timer_stress_all_with_rand_reset.69591067229655893985947723580938471607094588666351313852300988017723403597189
Line 375, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4199444826 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4199444826 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (aon_timer_scoreboard.sv:304) [scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (* [*] vs * [*]) has 1 failures:
- Test aon_timer_stress_all has 1 failures.
  - 38.aon_timer_stress_all.58009366862319413027566296301812006024784250673364962930927531997201439048657
    Line 310, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/38.aon_timer_stress_all/latest/run.log
```
  UVM_ERROR @ 217587996477 ps: (aon_timer_scoreboard.sv:304) [uvm_test_top.env.scoreboard] Check failed intr_status_exp[WKUP] === cfg.intr_vif.sample_pin(.idx(WKUP)) (0x1 [1] vs 0x0 [0])
  UVM_INFO @ 217587996477 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```