AON_TIMER Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.550s	530.827us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.460s	627.449us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.460s	540.021us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.860s	13.703ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.160s	553.289us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.450s	561.350us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.460s	540.021us	20	20	100.00
		aon_timer_csr_aliasing	1.160s	553.289us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.840s	434.279us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.120s	335.904us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.490m	61.370ms	50	50	100.00
V2	jump	aon_timer_jump	1.560s	590.461us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.641m	814.082ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.340s	516.752us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.710s	1.013ms	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.710s	1.013ms	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.460s	627.449us	5	5	100.00
		aon_timer_csr_rw	1.460s	540.021us	20	20	100.00
		aon_timer_csr_aliasing	1.160s	553.289us	5	5	100.00
		aon_timer_same_csr_outstanding	8.620s	2.680ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.460s	627.449us	5	5	100.00
		aon_timer_csr_rw	1.460s	540.021us	20	20	100.00
		aon_timer_csr_aliasing	1.160s	553.289us	5	5	100.00
		aon_timer_same_csr_outstanding	8.620s	2.680ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	10.770s	8.127ms	5	5	100.00
		aon_timer_tl_intg_err	13.360s	7.664ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.360s	7.664ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.170s	21.316ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			425	430	98.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
88.78	99.33	93.67	100.00	--	98.40	99.51	41.79

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 5 failures:

Test aon_timer_stress_all_with_rand_reset has 4 failures.

17.aon_timer_stress_all_with_rand_reset.27106455535494326664277162392589830771759005713432810875243865329335883958006
Line 357, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3989401243 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3989401243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

20.aon_timer_stress_all_with_rand_reset.59829903712037765193102215824380075139711517579204614388802687369002927900272
Line 292, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1064083672 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1064083672 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all has 1 failures.

49.aon_timer_stress_all.62439045187212397929581176331322320498756574502701121486993705847006014623945
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 146029232905 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 146029232905 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---