AON_TIMER Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.520s	612.919us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.410s	1.160ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.420s	512.264us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.200s	7.080ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.580s	617.908us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.300s	483.985us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.420s	512.264us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	617.908us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.300s	493.258us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.000s	400.535us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.317m	56.647ms	50	50	100.00
V2	jump	aon_timer_jump	1.510s	579.369us	50	50	100.00
V2	stress_all	aon_timer_stress_all	11.317m	442.291ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.280s	502.650us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.120s	638.099us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.120s	638.099us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.410s	1.160ms	5	5	100.00
		aon_timer_csr_rw	1.420s	512.264us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	617.908us	5	5	100.00
		aon_timer_same_csr_outstanding	5.230s	2.622ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.410s	1.160ms	5	5	100.00
		aon_timer_csr_rw	1.420s	512.264us	20	20	100.00
		aon_timer_csr_aliasing	1.580s	617.908us	5	5	100.00
		aon_timer_same_csr_outstanding	5.230s	2.622ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	7.290s	4.162ms	5	5	100.00
		aon_timer_tl_intg_err	13.810s	8.123ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.810s	8.123ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.101m	25.551ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.96	99.33	95.61	100.00	--	98.40	99.51	46.94

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all has 2 failures.

6.aon_timer_stress_all.93130630232170849157668219438416338109505337538389416506744145151244273394117
Line 317, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/6.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 151067323166 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 151067323166 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

47.aon_timer_stress_all.28448552936985432348458014854871994365528926842555256775496730964537559964426
Line 253, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/47.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 733236631 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 733236631 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all_with_rand_reset has 2 failures.

13.aon_timer_stress_all_with_rand_reset.108659901833478720285066078031237075491053070563088595410062666626705026496507
Line 336, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6046997578 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6046997578 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

42.aon_timer_stress_all_with_rand_reset.895144596322190034720633904804201930254856629925207997913112960024887786120
Line 329, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2283525192 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2283525192 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---