AON_TIMER Simulation Results

Saturday August 17 2024 23:02:17 UTC

GitHub Revision: `76588857da`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 94235727392619910305578226901221990521512464990339520078429467885466612377995

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.470s	600.026us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.420s	1.436ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.300s	480.572us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	13.270s	6.949ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.620s	639.171us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.310s	515.362us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.300s	480.572us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	639.171us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.130s	459.411us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.990s	287.204us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.315m	60.430ms	50	50	100.00
V2	jump	aon_timer_jump	1.450s	578.034us	50	50	100.00
V2	stress_all	aon_timer_stress_all	6.473m	239.847ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.280s	496.788us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.920s	572.651us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.920s	572.651us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.420s	1.436ms	5	5	100.00
		aon_timer_csr_rw	1.300s	480.572us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	639.171us	5	5	100.00
		aon_timer_same_csr_outstanding	8.630s	2.262ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.420s	1.436ms	5	5	100.00
		aon_timer_csr_rw	1.300s	480.572us	20	20	100.00
		aon_timer_csr_aliasing	1.620s	639.171us	5	5	100.00
		aon_timer_same_csr_outstanding	8.630s	2.262ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	7.200s	4.443ms	5	5	100.00
		aon_timer_tl_intg_err	15.120s	8.521ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	15.120s	8.521ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.380s	9.571ms	48	50	96.00
V3		TOTAL			48	50	96.00
		TOTAL			427	430	99.30

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.50	99.33	95.61	100.00	--	98.40	99.51	44.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 3 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

11.aon_timer_stress_all_with_rand_reset.59043912836235455655225157787955930963973507796267513047931757320366046177860
Line 421, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 7904522872 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 7904522872 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

49.aon_timer_stress_all_with_rand_reset.106947028838926623463542343531502379910133553630383927849280354984740222376177
Line 309, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/49.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2941510443 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2941510443 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 1 failures.

27.aon_timer_stress_all.65445303683099047423622341312155894898288860666264115159905589222675680007931
Line 297, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/27.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 8198087534 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 8198087534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---