AON_TIMER Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: `f1535c5540`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.440s	595.965us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.560s	695.927us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.310s	495.766us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	20.100s	7.138ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.830s	705.063us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.530s	460.255us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.310s	495.766us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	705.063us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	0.970s	309.337us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.020s	308.401us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.405m	53.978ms	50	50	100.00
V2	jump	aon_timer_jump	1.450s	617.792us	50	50	100.00
V2	stress_all	aon_timer_stress_all	14.148m	599.654ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	1.270s	475.549us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.850s	576.806us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.850s	576.806us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.560s	695.927us	5	5	100.00
		aon_timer_csr_rw	1.310s	495.766us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	705.063us	5	5	100.00
		aon_timer_same_csr_outstanding	6.250s	2.855ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.560s	695.927us	5	5	100.00
		aon_timer_csr_rw	1.310s	495.766us	20	20	100.00
		aon_timer_csr_aliasing	1.830s	705.063us	5	5	100.00
		aon_timer_same_csr_outstanding	6.250s	2.855ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	7.560s	4.493ms	5	5	100.00
		aon_timer_tl_intg_err	13.590s	8.723ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	13.590s	8.723ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.370s	9.523ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			420	430	97.67

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.35	99.33	95.61	100.00	--	98.40	99.51	43.27

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 10 failures:

Test aon_timer_stress_all has 4 failures.

10.aon_timer_stress_all.55875085095011437263678737221911644216147027503666892643621415455793685907307
Line 293, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/10.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 86115508953 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 86115508953 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all.110893273309868426080200805245866871100808552716126254803299000870148232641869
Line 305, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 147616454834 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 147616454834 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 6 failures.

12.aon_timer_stress_all_with_rand_reset.41839643208196781879888012402299333905883736510303188522317410284916141969372
Line 324, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1747160829 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1747160829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.aon_timer_stress_all_with_rand_reset.70712506604894124615830714958758711698414879063530368675060438556889599158087
Line 259, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/18.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 722473255 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 722473255 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.