AON_TIMER Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: `e45ccd274a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.560s	570.991us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.400s	1.197ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.310s	507.043us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	10.690s	14.355ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.450s	532.811us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.460s	558.210us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.310s	507.043us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	532.811us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.070s	418.329us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.200s	498.834us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.481m	59.195ms	50	50	100.00
V2	jump	aon_timer_jump	1.540s	590.189us	50	50	100.00
V2	stress_all	aon_timer_stress_all	9.082m	367.593ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	1.300s	503.481us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	3.290s	537.710us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	3.290s	537.710us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.400s	1.197ms	5	5	100.00
		aon_timer_csr_rw	1.310s	507.043us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	532.811us	5	5	100.00
		aon_timer_same_csr_outstanding	5.100s	2.394ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.400s	1.197ms	5	5	100.00
		aon_timer_csr_rw	1.310s	507.043us	20	20	100.00
		aon_timer_csr_aliasing	1.450s	532.811us	5	5	100.00
		aon_timer_same_csr_outstanding	5.100s	2.394ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.320s	7.735ms	5	5	100.00
		aon_timer_tl_intg_err	14.220s	8.544ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	14.220s	8.544ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	45.630s	5.212ms	44	50	88.00
V3		TOTAL			44	50	88.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.72	99.33	95.61	100.00	--	98.40	99.51	45.48

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 7 failures:

Test aon_timer_stress_all_with_rand_reset has 6 failures.

12.aon_timer_stress_all_with_rand_reset.81193895265375426198573593600216755481789704548505471062440884225101466879259
Line 294, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/12.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1946650609 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1946650609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

24.aon_timer_stress_all_with_rand_reset.73930735493003845493305437288978343122233447666246650189627921031435602627688
Line 419, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 3688649176 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 3688649176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

Test aon_timer_stress_all has 1 failures.

22.aon_timer_stress_all.99256993378636998465964956415277637050879181894912817140640297111657938821280
Line 313, in log /container/opentitan-public/scratch/os_regression/aon_timer-sim-vcs/22.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 14569554405 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 14569554405 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---