AON_TIMER Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.770s	583.235us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.550s	1.059ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.280s	429.757us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	7.700s	13.843ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.190s	537.413us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.100s	418.917us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.280s	429.757us	20	20	100.00
		aon_timer_csr_aliasing	2.190s	537.413us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.370s	384.046us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.310s	477.784us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.482m	55.097ms	50	50	100.00
V2	jump	aon_timer_jump	2.760s	544.274us	50	50	100.00
V2	stress_all	aon_timer_stress_all	17.181m	529.686ms	48	50	96.00
V2	intr_test	aon_timer_intr_test	1.670s	341.049us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.960s	848.044us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.960s	848.044us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.550s	1.059ms	5	5	100.00
		aon_timer_csr_rw	2.280s	429.757us	20	20	100.00
		aon_timer_csr_aliasing	2.190s	537.413us	5	5	100.00
		aon_timer_same_csr_outstanding	6.470s	2.198ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.550s	1.059ms	5	5	100.00
		aon_timer_csr_rw	2.280s	429.757us	20	20	100.00
		aon_timer_csr_aliasing	2.190s	537.413us	5	5	100.00
		aon_timer_same_csr_outstanding	6.470s	2.198ms	20	20	100.00
V2		TOTAL			238	240	99.17
V2S	tl_intg_err	aon_timer_sec_cm	19.120s	8.261ms	5	5	100.00
		aon_timer_tl_intg_err	11.420s	8.181ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	11.420s	8.181ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.273m	13.012ms	45	50	90.00
V3		TOTAL			45	50	90.00
		TOTAL			423	430	98.37

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.67	99.33	95.61	100.00	--	98.40	99.51	45.15

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 6 failures:

Test aon_timer_stress_all_with_rand_reset has 4 failures.

3.aon_timer_stress_all_with_rand_reset.66107777674394865228312580960850117936630183379519835342624016034996404055899
Line 122, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/3.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1807434787 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1807434787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

17.aon_timer_stress_all_with_rand_reset.2277726769886658511899561535912095347119817566098693644883289771851669570637
Line 275, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/17.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 4987444095 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 4987444095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all has 2 failures.

15.aon_timer_stress_all.12683459911396273614332773851268306001355241346783329944662789409482118298529
Line 142, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/15.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 16139609290 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16139609290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.aon_timer_stress_all.81649126378329998619425905955592764041394164872409698951018509614807551480993
Line 106, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/23.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2796363980 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2796363980 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:771) [aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 24.aon_timer_stress_all_with_rand_reset.85617972926206853938203787577227040387876227689533483721608482257483001758200
    Line 92, in log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 627386213 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 627386213 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```