AON_TIMER Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	1.230s	545.131us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	1.890s	1.133ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	1.160s	498.688us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	9.340s	6.908ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	1.530s	519.948us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	1.200s	473.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	1.160s	498.688us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	519.948us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.000s	495.174us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	0.750s	478.052us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.263m	61.115ms	50	50	100.00
V2	jump	aon_timer_jump	1.430s	488.072us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.535m	482.499ms	45	50	90.00
V2	intr_test	aon_timer_intr_test	1.140s	480.001us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	2.160s	479.648us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	2.160s	479.648us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	1.890s	1.133ms	5	5	100.00
		aon_timer_csr_rw	1.160s	498.688us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	519.948us	5	5	100.00
		aon_timer_same_csr_outstanding	5.780s	2.544ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	1.890s	1.133ms	5	5	100.00
		aon_timer_csr_rw	1.160s	498.688us	20	20	100.00
		aon_timer_csr_aliasing	1.530s	519.948us	5	5	100.00
		aon_timer_same_csr_outstanding	5.780s	2.544ms	20	20	100.00
V2		TOTAL			235	240	97.92
V2S	tl_intg_err	aon_timer_sec_cm	3.230s	8.115ms	5	5	100.00
		aon_timer_tl_intg_err	12.440s	8.964ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	12.440s	8.964ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	47.190s	70.949ms	46	50	92.00
V3		TOTAL			46	50	92.00
		TOTAL			421	430	97.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.61	99.33	95.61	100.00	--	98.40	99.51	44.84

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 9 failures:

Test aon_timer_stress_all has 5 failures.

16.aon_timer_stress_all.24292471487867182850084074699471242702879969314163776652098278173552799901837
Line 70, in log /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/16.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 1041114203 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1041114203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.aon_timer_stress_all.37460773852255144116022757867950820716431949072593799447719219103095495463035
Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/30.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 55646075741 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 55646075741 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test aon_timer_stress_all_with_rand_reset has 4 failures.

24.aon_timer_stress_all_with_rand_reset.98897121110935703848245640628406490114164699149879747172926574690258185758598
Line 262, in log /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/24.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 6129516194 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 6129516194 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.aon_timer_stress_all_with_rand_reset.16108150780073409336232743301650594442133203511480198377213727868452621239102
Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_22/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 661326336 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 661326336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.