AON_TIMER Simulation Results

Saturday August 24 2024 20:58:08 UTC

GitHub Revision: `e733a8ef8a`

Branch: os_regression_2024_08_24

Simulator: VCS

Build randomization enabled with --build-seed 36240513409906943553650221581975102764006655953510936167454320581301243659163

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.760s	547.525us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.810s	670.238us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.740s	547.410us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	47.740s	9.209ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	3.530s	647.726us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.550s	497.374us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.740s	547.410us	20	20	100.00
		aon_timer_csr_aliasing	3.530s	647.726us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.760s	517.438us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.370s	447.502us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	2.816m	61.548ms	50	50	100.00
V2	jump	aon_timer_jump	2.800s	556.288us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.101m	501.848ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	2.500s	503.184us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.340s	761.150us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.340s	761.150us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.810s	670.238us	5	5	100.00
		aon_timer_csr_rw	2.740s	547.410us	20	20	100.00
		aon_timer_csr_aliasing	3.530s	647.726us	5	5	100.00
		aon_timer_same_csr_outstanding	11.200s	2.379ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.810s	670.238us	5	5	100.00
		aon_timer_csr_rw	2.740s	547.410us	20	20	100.00
		aon_timer_csr_aliasing	3.530s	647.726us	5	5	100.00
		aon_timer_same_csr_outstanding	11.200s	2.379ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	17.660s	4.477ms	5	5	100.00
		aon_timer_tl_intg_err	26.450s	7.728ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	26.450s	7.728ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	1.199m	17.965ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.07	99.33	95.61	100.00	--	98.40	99.51	47.58

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all has 3 failures.

12.aon_timer_stress_all.87473612523748049341908936730047517525050078276382725955654201809064832444227
Line 94, in log /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/12.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 90087786550 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 90087786550 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.aon_timer_stress_all.98897230169408979827071036369824394198011118090802747412893572517736324031971
Line 110, in log /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/29.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 67303427657 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 67303427657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 1 failures.

42.aon_timer_stress_all_with_rand_reset.48640546961096609669158912030504403803530468200697367881539157120281169617856
Line 101, in log /workspaces/repo/scratch/os_regression_2024_08_24/aon_timer-sim-vcs/42.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 1525740051 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 1525740051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---