AON_TIMER Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: `4674f625b3`

Branch: os_regression_2024_08_26

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.390s	563.666us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	2.960s	1.276ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.160s	431.726us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	30.340s	11.673ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.750s	489.457us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.770s	523.558us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.160s	431.726us	20	20	100.00
		aon_timer_csr_aliasing	2.750s	489.457us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.510s	481.768us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.910s	361.708us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.895m	46.809ms	50	50	100.00
V2	jump	aon_timer_jump	3.050s	586.403us	50	50	100.00
V2	stress_all	aon_timer_stress_all	19.837m	675.023ms	47	50	94.00
V2	intr_test	aon_timer_intr_test	2.180s	423.785us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.370s	422.485us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.370s	422.485us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	2.960s	1.276ms	5	5	100.00
		aon_timer_csr_rw	2.160s	431.726us	20	20	100.00
		aon_timer_csr_aliasing	2.750s	489.457us	5	5	100.00
		aon_timer_same_csr_outstanding	5.720s	2.313ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	2.960s	1.276ms	5	5	100.00
		aon_timer_csr_rw	2.160s	431.726us	20	20	100.00
		aon_timer_csr_aliasing	2.750s	489.457us	5	5	100.00
		aon_timer_same_csr_outstanding	5.720s	2.313ms	20	20	100.00
V2		TOTAL			237	240	98.75
V2S	tl_intg_err	aon_timer_sec_cm	13.490s	7.871ms	5	5	100.00
		aon_timer_tl_intg_err	18.530s	7.640ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	18.530s	7.640ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	59.210s	6.028ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.75	99.33	95.61	100.00	--	98.40	99.51	45.64

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 4 failures:

Test aon_timer_stress_all has 3 failures.

11.aon_timer_stress_all.70581361951994245253367048784989285950624968113240425020205202758769668308601
Line 82, in log /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/11.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 2004271780 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2004271780 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.aon_timer_stress_all.46951446966406761483889239117688106085799700379137301228233462250768331514633
Line 66, in log /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/35.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 771139704 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 771139704 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test aon_timer_stress_all_with_rand_reset has 1 failures.

21.aon_timer_stress_all_with_rand_reset.36968059209962091146525909338444563326050299613911019625308992663286887735318
Line 72, in log /workspaces/repo/scratch/os_regression_2024_08_26/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 684762210 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 684762210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---