a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 2.560s | 598.679us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 1.820s | 998.376us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 2.570s | 546.191us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 8.790s | 7.241ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 2.410s | 643.046us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 2.460s | 440.303us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 2.570s | 546.191us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 2.410s | 643.046us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.590s | 349.016us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 2.330s | 477.548us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 2.059m | 59.841ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 3.130s | 593.066us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 10.387m | 346.126ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 2.410s | 496.299us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 3.460s | 397.245us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 3.460s | 397.245us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 1.820s | 998.376us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.570s | 546.191us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.410s | 643.046us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.730s | 2.084ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 1.820s | 998.376us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.570s | 546.191us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.410s | 643.046us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.730s | 2.084ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 6.070s | 3.887ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 21.990s | 8.365ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 21.990s | 8.365ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 1.060m | 9.256ms | 42 | 50 | 84.00 |
| V3 | TOTAL | 42 | 50 | 84.00 | |||
| TOTAL | 422 | 430 | 98.14 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.02 | 99.33 | 95.61 | 100.00 | -- | 98.40 | 99.51 | 41.28 |
UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 8 failures:
11.aon_timer_stress_all_with_rand_reset.14394305669092068184038660684015066611405437576250885906618903145583781451076
Line 75, in log /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/11.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 628966819 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 628966819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.aon_timer_stress_all_with_rand_reset.77499689397200367844131011497071617321496666963318226925162673997762925096420
Line 195, in log /workspaces/repo/scratch/os_regression_2024_08_28/aon_timer-sim-vcs/13.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 3319651677 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 3319651677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.