ed1c41cd0f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | aon_timer_smoke | 2.450s | 452.909us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | aon_timer_csr_hw_reset | 2.270s | 688.643us | 5 | 5 | 100.00 |
| V1 | csr_rw | aon_timer_csr_rw | 2.670s | 484.783us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | aon_timer_csr_bit_bash | 21.050s | 11.852ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | aon_timer_csr_aliasing | 2.370s | 581.564us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | aon_timer_csr_mem_rw_with_rand_reset | 2.730s | 515.482us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | aon_timer_csr_rw | 2.670s | 484.783us | 20 | 20 | 100.00 |
| aon_timer_csr_aliasing | 2.370s | 581.564us | 5 | 5 | 100.00 | ||
| V1 | mem_walk | aon_timer_mem_walk | 1.780s | 331.494us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | aon_timer_mem_partial_access | 2.090s | 512.342us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | prescaler | aon_timer_prescaler | 2.084m | 56.555ms | 50 | 50 | 100.00 |
| V2 | jump | aon_timer_jump | 2.640s | 475.894us | 50 | 50 | 100.00 |
| V2 | stress_all | aon_timer_stress_all | 21.539m | 743.541ms | 50 | 50 | 100.00 |
| V2 | intr_test | aon_timer_intr_test | 2.280s | 488.042us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | aon_timer_tl_errors | 4.380s | 402.574us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | aon_timer_tl_errors | 4.380s | 402.574us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | aon_timer_csr_hw_reset | 2.270s | 688.643us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.670s | 484.783us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.370s | 581.564us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.890s | 2.221ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | aon_timer_csr_hw_reset | 2.270s | 688.643us | 5 | 5 | 100.00 |
| aon_timer_csr_rw | 2.670s | 484.783us | 20 | 20 | 100.00 | ||
| aon_timer_csr_aliasing | 2.370s | 581.564us | 5 | 5 | 100.00 | ||
| aon_timer_same_csr_outstanding | 8.890s | 2.221ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 240 | 240 | 100.00 | |||
| V2S | tl_intg_err | aon_timer_sec_cm | 11.340s | 7.965ms | 5 | 5 | 100.00 |
| aon_timer_tl_intg_err | 10.820s | 8.054ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | aon_timer_tl_intg_err | 10.820s | 8.054ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | aon_timer_stress_all_with_rand_reset | 59.050s | 44.052ms | 45 | 50 | 90.00 |
| V3 | TOTAL | 45 | 50 | 90.00 | |||
| TOTAL | 425 | 430 | 98.84 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 6 | 6 | 6 | 100.00 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 89.28 | 99.33 | 95.61 | 100.00 | -- | 98.40 | 99.51 | 42.83 |
UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 5 failures:
20.aon_timer_stress_all_with_rand_reset.33563392222165483844701298075156033296191241462181760871863403075023163605931
Line 107, in log /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/20.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7231268724 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 7231268724 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
21.aon_timer_stress_all_with_rand_reset.66585352579154670886484638065595317619090139893009050385572549883299388402055
Line 130, in log /workspaces/repo/scratch/os_regression_2024_08_31/aon_timer-sim-vcs/21.aon_timer_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1909290758 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
UVM_INFO @ 1909290758 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.