AON_TIMER Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: `372a6306e0`

Branch: os_regression_2024_09_03

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.940s	594.649us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	3.690s	962.735us	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.380s	512.767us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	19.050s	7.187ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.470s	440.608us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.620s	523.804us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.380s	512.767us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	440.608us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.640s	315.321us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	1.700s	278.457us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	2.179m	56.059ms	50	50	100.00
V2	jump	aon_timer_jump	2.770s	544.701us	50	50	100.00
V2	stress_all	aon_timer_stress_all	10.420m	311.597ms	46	50	92.00
V2	intr_test	aon_timer_intr_test	2.620s	486.682us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	5.700s	591.790us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	5.700s	591.790us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	3.690s	962.735us	5	5	100.00
		aon_timer_csr_rw	2.380s	512.767us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	440.608us	5	5	100.00
		aon_timer_same_csr_outstanding	11.470s	2.314ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	3.690s	962.735us	5	5	100.00
		aon_timer_csr_rw	2.380s	512.767us	20	20	100.00
		aon_timer_csr_aliasing	2.470s	440.608us	5	5	100.00
		aon_timer_same_csr_outstanding	11.470s	2.314ms	20	20	100.00
V2		TOTAL			236	240	98.33
V2S	tl_intg_err	aon_timer_sec_cm	25.120s	8.464ms	5	5	100.00
		aon_timer_tl_intg_err	25.480s	8.103ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	25.480s	8.103ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	51.830s	5.901ms	43	50	86.00
V3		TOTAL			43	50	86.00
		TOTAL			419	430	97.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.08	99.33	95.61	100.00	--	98.40	99.51	41.61

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state

has 11 failures:

Test aon_timer_stress_all has 4 failures.

2.aon_timer_stress_all.85184123839403912089891682775637813527530923616375109774407766514781455375458
Line 122, in log /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/2.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 311597026586 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 311597026586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.aon_timer_stress_all.65315088567048071803563024028539890515647574046872668745875793835159316137882
Line 74, in log /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/22.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 535836781 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 535836781 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Test aon_timer_stress_all_with_rand_reset has 7 failures.

14.aon_timer_stress_all_with_rand_reset.77137095102105094045708474081376406179392943794357084211907804756137333002174
Line 201, in log /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/14.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 5720326175 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 5720326175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.aon_timer_stress_all_with_rand_reset.10134092484041066119076325100832400087238404768564867903916638373459724083191
Line 140, in log /workspaces/repo/scratch/os_regression_2024_09_03/aon_timer-sim-vcs/15.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 2320438891 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 2320438891 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.