AON_TIMER Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	aon_timer_smoke	2.890s	588.308us	50	50	100.00
V1	csr_hw_reset	aon_timer_csr_hw_reset	4.860s	1.147ms	5	5	100.00
V1	csr_rw	aon_timer_csr_rw	2.380s	508.216us	20	20	100.00
V1	csr_bit_bash	aon_timer_csr_bit_bash	23.280s	7.277ms	5	5	100.00
V1	csr_aliasing	aon_timer_csr_aliasing	2.200s	390.045us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	aon_timer_csr_mem_rw_with_rand_reset	2.640s	564.871us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	aon_timer_csr_rw	2.380s	508.216us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	390.045us	5	5	100.00
V1	mem_walk	aon_timer_mem_walk	1.980s	362.691us	5	5	100.00
V1	mem_partial_access	aon_timer_mem_partial_access	2.490s	496.340us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	prescaler	aon_timer_prescaler	1.584m	54.837ms	50	50	100.00
V2	jump	aon_timer_jump	2.840s	561.771us	50	50	100.00
V2	stress_all	aon_timer_stress_all	20.962m	650.406ms	49	50	98.00
V2	intr_test	aon_timer_intr_test	2.370s	515.527us	50	50	100.00
V2	tl_d_oob_addr_access	aon_timer_tl_errors	4.640s	480.853us	20	20	100.00
V2	tl_d_illegal_access	aon_timer_tl_errors	4.640s	480.853us	20	20	100.00
V2	tl_d_outstanding_access	aon_timer_csr_hw_reset	4.860s	1.147ms	5	5	100.00
		aon_timer_csr_rw	2.380s	508.216us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	390.045us	5	5	100.00
		aon_timer_same_csr_outstanding	7.730s	2.418ms	20	20	100.00
V2	tl_d_partial_access	aon_timer_csr_hw_reset	4.860s	1.147ms	5	5	100.00
		aon_timer_csr_rw	2.380s	508.216us	20	20	100.00
		aon_timer_csr_aliasing	2.200s	390.045us	5	5	100.00
		aon_timer_same_csr_outstanding	7.730s	2.418ms	20	20	100.00
V2		TOTAL			239	240	99.58
V2S	tl_intg_err	aon_timer_sec_cm	13.550s	4.346ms	5	5	100.00
		aon_timer_tl_intg_err	26.050s	7.690ms	20	20	100.00
V2S	sec_cm_bus_integrity	aon_timer_tl_intg_err	26.050s	7.690ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	aon_timer_stress_all_with_rand_reset	53.790s	33.066ms	47	50	94.00
V3		TOTAL			47	50	94.00
		TOTAL			426	430	99.07

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	6	6	5	83.33
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.64	99.33	95.61	100.00	--	98.40	99.51	45.02

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:471) [aon_timer_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRaon_timer_reg_block.intr_state has 3 failures:

Test aon_timer_stress_all_with_rand_reset has 2 failures.

1.aon_timer_stress_all_with_rand_reset.40749446920184488706614058096449538872670416870260076134213358287975167274854
Line 361, in log /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/1.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 16317225584 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 2 [0x2]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 16317225584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

45.aon_timer_stress_all_with_rand_reset.79694414019569610675810687064931195645266843254049833291493286032697079426590
Line 77, in log /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/45.aon_timer_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 612657058 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (2 [0x2] vs 3 [0x3]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 612657058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test aon_timer_stress_all has 1 failures.

14.aon_timer_stress_all.31051926160877549411278396990316123976104742504181754602694094081627095512438
Line 86, in log /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/14.aon_timer_stress_all/latest/run.log

  UVM_ERROR @ 19881719042 ps: (cip_base_vseq.sv:471) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1 [0x1]) when reading the intr CSRaon_timer_reg_block.intr_state
  UVM_INFO @ 19881719042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_vseq.sv:771) [aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test aon_timer_stress_all_with_rand_reset has 1 failures.
  - 27.aon_timer_stress_all_with_rand_reset.66050343667641487753466017971244828835917033135301901087675226652112816831122
    Line 244, in log /workspaces/repo/scratch/os_regression_2024_09_08/aon_timer-sim-vcs/27.aon_timer_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 7585561540 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.aon_timer_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 7585561540 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```