FLASH_CTRL Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.233m	43.800us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.270s	15.599us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.770s	26.417us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.329m	4.866ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.150m	14.437ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.280s	44.064us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.150m	14.437ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.520s	61.767us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.510s	56.161us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.640s	75.532us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.884m	223.626us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	27.072m	146.116ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.203m	420.311ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.580s	128.740us	19	20	95.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.601m	285.135ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.740m	11.223ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.302m	10.017ms	28	30	93.33
V2	full_memory_access	flash_ctrl_full_mem_access	45.919m	366.484ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.280m	5.654ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.220s	380.574us	39	40	97.50
		flash_ctrl_rw_evict_all_en	34.780s	491.237us	40	40	100.00
		flash_ctrl_re_evict	41.400s	551.813us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.885m	4.082ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.885m	4.082ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.379m	66.306ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	25.440s	149.390us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	19.585m	4.666ms	19	20	95.00
V2	error_mp	flash_ctrl_error_mp	42.391m	12.833ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.399m	1.380ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.709m	2.715ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.800s	25.876us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.430m	2.490ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.710s	13.694us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.710s	18.545us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.015m	3.762ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.355m	8.608ms	50	50	100.00
		flash_ctrl_otp_reset	2.256m	598.999us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	27.072m	146.116ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	6.196m	3.529ms	40	40	100.00
		flash_ctrl_intr_wr	2.078m	5.043ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.426m	130.936ms	37	40	92.50
		flash_ctrl_intr_wr_slow_flash	8.930m	193.136ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	1.539m	7.064ms	15	20	75.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	34.480s	5.253ms	4	5	80.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.720s	19.473us	5	5	100.00
		flash_ctrl_ro_derr	5.553m	3.582ms	10	10	100.00
		flash_ctrl_rw_derr	26.105m	6.232ms	10	10	100.00
		flash_ctrl_derr_detect	1.856m	145.787us	5	5	100.00
		flash_ctrl_integrity	29.616m	7.573ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.180s	24.658us	5	5	100.00
		flash_ctrl_ro_serr	5.262m	1.782ms	10	10	100.00
		flash_ctrl_rw_serr	26.187m	20.894ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.201m	624.734us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.895m	1.171ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.350m	4.847ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.270s	63.666us	1	1	100.00
		flash_ctrl_read_word_sweep	13.320s	68.928us	1	1	100.00
		flash_ctrl_ro	4.835m	4.619ms	20	20	100.00
		flash_ctrl_rw	21.909m	41.406ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	35.770s	627.963us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.103m	98.617ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.633m	10.019ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.250s	419.210us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.550s	17.573us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.100s	331.696us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.100s	331.696us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.770s	26.417us	5	5	100.00
		flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.150m	14.437ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.950s	312.436us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.770s	26.417us	5	5	100.00
		flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
		flash_ctrl_csr_aliasing	1.150m	14.437ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	34.950s	312.436us	20	20	100.00
V2		TOTAL			998	1013	98.52
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	1.716m	128.768us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.280m	5.786ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.280m	5.786ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.280m	5.786ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.300s	70.834us	2	3	66.67
		flash_ctrl_wr_intg	14.550s	47.255us	2	3	66.67
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.233m	43.800us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.256m	598.999us	80	80	100.00
		flash_ctrl_disable	22.710s	13.694us	50	50	100.00
		flash_ctrl_sec_info_access	1.517m	19.645ms	50	50	100.00
		flash_ctrl_connect	16.710s	18.545us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.940s	29.211us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.120s	1.278ms	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	1.958m	560.126us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.710s	13.694us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.300s	70.834us	2	3	66.67
		flash_ctrl_access_after_disable	13.550s	182.170us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.710s	13.694us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	25.440s	149.390us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	21.909m	41.406ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	26.187m	20.894ms	10	10	100.00
		flash_ctrl_rw_derr	26.105m	6.232ms	10	10	100.00
		flash_ctrl_integrity	29.616m	7.573ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	27.072m	146.116ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.560s	25.735us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.790s	42.661us	1	5	20.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.660s	25.424us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.349h	1.357ms	5	5	100.00
V2S		TOTAL			137	144	95.14
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.730s	381.109us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1256	1278	98.28

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	47	85.45
V2S	12	12	8	66.67
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.51	95.49	94.38	98.95	92.52	97.34	98.30	98.62

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 4 failures:

Test flash_ctrl_invalid_op has 4 failures.

0.flash_ctrl_invalid_op.3766276590
Line 751, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 630749.7 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 630749.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_invalid_op.3141450801
Line 2142, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 327843.1 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 327843.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

Offending '(!$isunknown(mem_tl_o.d_valid))' has 4 failures:

Test flash_ctrl_phy_host_grant_err has 4 failures.

0.flash_ctrl_phy_host_grant_err.3951335306
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 23918.4 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 23918.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_phy_host_grant_err.51498054
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 20965.0 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 20965.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 4 failures:

Test flash_ctrl_intr_rd_slow_flash has 3 failures.

1.flash_ctrl_intr_rd_slow_flash.2882406538
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_intr_rd_slow_flash.4272613372
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test flash_ctrl_intr_wr_slow_flash has 1 failures.

9.flash_ctrl_intr_wr_slow_flash.4055303404
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_rd_path_intg_vseq.sv:59) [flash_ctrl_rd_path_intg_vseq] Check failed saw_err == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_rd_intg has 1 failures.
  - 0.flash_ctrl_rd_intg.2527079270
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest/run.log
```
  UVM_ERROR @ 18637.9 ns: (flash_ctrl_rd_path_intg_vseq.sv:59) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rd_path_intg_vseq] Check failed saw_err == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 18637.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0] *: obs:exp *_d_7191e6c8_ffffffff:5b_c_549e656c_f4ac* mismatch!! has 1 failures:
- Test flash_ctrl_wr_intg has 1 failures.
  - 0.flash_ctrl_wr_intg.1807046797
    Line 268, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest/run.log
```
  UVM_ERROR @ 26787.5 ns: (flash_ctrl_otf_scoreboard.sv:365) [wdata_page0_comp_bank0]    0: obs:exp    84_d_7191e6c8_ffffffff:5b_c_549e656c_f4ac4519  mismatch!!
  UVM_INFO @ 26787.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (* [*] vs * [*]) Memory model check failed in partition FlashPartInfo*, bank *, addr * (*) has 1 failures:
- Test flash_ctrl_rand_ops has 1 failures.
  - 1.flash_ctrl_rand_ops.670043821
    Line 268623, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest/run.log
```
  UVM_ERROR @ 3476068.1 ns: (flash_ctrl_env_cfg.sv:434) [cfg] Check failed bkdr_rd_data == scb_flash_model[addr] (4294967295 [0xffffffff] vs 3906572531 [0xe8d990f3]) Memory model check failed in partition FlashPartInfo1, bank 1, addr 0x1c0 (448)
  UVM_INFO @ 3476068.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$past(clr_i)' has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 1.flash_ctrl_phy_ack_consistency.1738585634
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest/run.log
```
      Offending '$past(clr_i)'
  UVM_ERROR @ 25288.5 ns: (prim_count.sv:167) [ASSERT FAILED] ClrBkwd_A
  UVM_INFO @ 25288.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (csr_utils_pkg.sv:620) [csr_utils::mem_rd] Timeout waiting to mem_rd flash_ctrl_core_reg_block.rd_fifo (addr=*) has 1 failures:
- Test flash_ctrl_mid_op_rst has 1 failures.
  - 2.flash_ctrl_mid_op_rst.2703897533
    Line 721, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest/run.log
```
  UVM_FATAL @ 5253170.6 ns: (csr_utils_pkg.sv:620) [csr_utils::mem_rd] Timeout waiting to mem_rd flash_ctrl_core_reg_block.rd_fifo (addr=0x0)
  UVM_INFO @ 5253170.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_prog_reset_vseq.sv:76) [flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPostPack has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 10.flash_ctrl_prog_reset.3196480456
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 10016959.4 ns: (flash_ctrl_prog_reset_vseq.sv:76) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Timed out waiting for DVStPostPack
  UVM_INFO @ 10016959.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 11.flash_ctrl_prog_reset.3651078019
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 9934.6 ns: (flash_ctrl_otf_scoreboard.sv:428) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].data_mem_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 9934.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_invalid_op has 1 failures.
  - 12.flash_ctrl_invalid_op.3423145764
    Line 2037, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest/run.log
```
  UVM_ERROR @ 1022622.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 1022622.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: * has 1 failures:
- Test flash_ctrl_lcmgr_intg has 1 failures.
  - 18.flash_ctrl_lcmgr_intg.631199340
    Line 264, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest/run.log
```
  UVM_ERROR @ 6926.9 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.std_fault_status.lcmgr_intg_err reset value: 0x0
  UVM_INFO @ 6926.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 20.flash_ctrl_rw_evict.3087270397
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 73837.9 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 73837.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```