213e792ea
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | gpio_smoke | 1.450s | 329.838us | 50 | 50 | 100.00 |
gpio_smoke_no_pullup_pulldown | 1.450s | 89.300us | 50 | 50 | 100.00 | ||
V1 | csr_hw_reset | gpio_csr_hw_reset | 0.690s | 21.791us | 5 | 5 | 100.00 |
V1 | csr_rw | gpio_csr_rw | 0.630s | 17.751us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | gpio_csr_bit_bash | 3.400s | 1.363ms | 5 | 5 | 100.00 |
V1 | csr_aliasing | gpio_csr_aliasing | 0.860s | 32.799us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.370s | 131.207us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.630s | 17.751us | 20 | 20 | 100.00 |
gpio_csr_aliasing | 0.860s | 32.799us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 155 | 155 | 100.00 | |||
V2 | direct_and_masked_out | gpio_random_dout_din | 1.330s | 248.560us | 50 | 50 | 100.00 |
gpio_random_dout_din_no_pullup_pulldown | 1.320s | 79.502us | 50 | 50 | 100.00 | ||
V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 1.040s | 43.455us | 50 | 50 | 100.00 |
V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.520s | 100.976us | 50 | 50 | 100.00 |
V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.510s | 1.335ms | 50 | 50 | 100.00 |
V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.720s | 404.771us | 50 | 50 | 100.00 |
V2 | noise_filter_stress | gpio_filter_stress | 26.850s | 1.065ms | 50 | 50 | 100.00 |
V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 5.760s | 480.763us | 50 | 50 | 100.00 |
V2 | full_random | gpio_full_random | 1.140s | 96.376us | 50 | 50 | 100.00 |
V2 | stress_all | gpio_stress_all | 3.637m | 313.494ms | 50 | 50 | 100.00 |
V2 | alert_test | gpio_alert_test | 0.620s | 67.234us | 50 | 50 | 100.00 |
V2 | intr_test | gpio_intr_test | 0.640s | 102.345us | 26 | 50 | 52.00 |
V2 | tl_d_oob_addr_access | gpio_tl_errors | 3.070s | 237.792us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | gpio_tl_errors | 3.070s | 237.792us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | gpio_csr_rw | 0.630s | 17.751us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.840s | 68.165us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.860s | 32.799us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.690s | 21.791us | 5 | 5 | 100.00 | ||
V2 | tl_d_partial_access | gpio_csr_rw | 0.630s | 17.751us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.840s | 68.165us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.860s | 32.799us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.690s | 21.791us | 5 | 5 | 100.00 | ||
V2 | TOTAL | 616 | 640 | 96.25 | |||
V2S | tl_intg_err | gpio_tl_intg_err | 1.600s | 595.451us | 20 | 20 | 100.00 |
gpio_sec_cm | 0.930s | 81.942us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.600s | 595.451us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 41.227m | 95.772ms | 50 | 50 | 100.00 |
V3 | TOTAL | 50 | 50 | 100.00 | |||
TOTAL | 846 | 870 | 97.24 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 7 | 7 | 7 | 100.00 |
V2 | 14 | 14 | 13 | 92.86 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 1 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.61 | 99.07 | 99.10 | 100.00 | -- | 99.80 | 99.68 | 100.00 |
UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state
has 24 failures:
0.gpio_intr_test.830696426
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_intr_test/latest/run.log
UVM_ERROR @ 1141224 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (0 [0x0] vs 1585114666 [0x5e7aee2a]) when reading the intr CSRgpio_reg_block.intr_state
UVM_INFO @ 1141224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.gpio_intr_test.3473840951
Line 218, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_test/latest/run.log
UVM_ERROR @ 9998446 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 2094722217 [0x7cdaeca9]) when reading the intr CSRgpio_reg_block.intr_state
UVM_INFO @ 9998446 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.