GPIO Simulation Results

Sunday May 28 2023 07:05:15 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2869101736

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.400s	160.491us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.490s	170.994us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.620s	56.854us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	49.729us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.310s	913.115us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.790s	14.152us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.510s	30.194us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	49.729us	20	20	100.00
		gpio_csr_aliasing	0.790s	14.152us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.340s	71.513us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.360s	56.903us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.000s	207.489us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.450s	133.408us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.850s	126.536us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.850s	183.919us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.220s	3.301ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.950s	390.540us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	202.321us	50	50	100.00
V2	stress_all	gpio_stress_all	4.033m	68.622ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	14.015us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	47.563us	28	50	56.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.000s	167.341us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.000s	167.341us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	49.729us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	72.776us	20	20	100.00
		gpio_csr_aliasing	0.790s	14.152us	5	5	100.00
		gpio_csr_hw_reset	0.620s	56.854us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	49.729us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	72.776us	20	20	100.00
		gpio_csr_aliasing	0.790s	14.152us	5	5	100.00
		gpio_csr_hw_reset	0.620s	56.854us	5	5	100.00
V2		TOTAL			618	640	96.56
V2S	tl_intg_err	gpio_tl_intg_err	1.550s	308.392us	20	20	100.00
		gpio_sec_cm	0.850s	276.276us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.550s	308.392us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	51.465m	504.461ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			848	870	97.47

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 22 failures:

Test gpio_intr_test has 22 failures.

1.gpio_intr_test.4197020243
Line 224, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_intr_test/latest/run.log

  UVM_ERROR @   7655313 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 3021986033 [0xb41fd8f1]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   7655313 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.gpio_intr_test.2331202545
Line 217, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/8.gpio_intr_test/latest/run.log

  UVM_ERROR @   1037853 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 4144417363 [0xf706ca53]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   1037853 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.