KMAC/MASKED Simulation Results

Wednesday May 24 2023 07:09:34 UTC

GitHub Revision: `26b0ee226`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 844256362

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.481m	13.615ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.250s	48.698us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.280s	302.524us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	23.610s	3.155ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	10.550s	1.608ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.380s	30.999us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.280s	302.524us	20	20	100.00
		kmac_csr_aliasing	10.550s	1.608ms	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.770s	13.603us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.440s	18.868us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	54.304m	479.232ms	50	50	100.00
V2	burst_write	kmac_burst_write	27.416m	52.563ms	49	50	98.00
V2	test_vectors	kmac_test_vectors_sha3_224	42.815m	203.460ms	50	50	100.00
		kmac_test_vectors_sha3_256	41.754m	762.861ms	50	50	100.00
		kmac_test_vectors_sha3_384	33.512m	362.345ms	50	50	100.00
		kmac_test_vectors_sha3_512	23.290m	198.581ms	49	50	98.00
		kmac_test_vectors_shake_128	1.849h	530.320ms	49	50	98.00
		kmac_test_vectors_shake_256	1.568h	790.674ms	48	50	96.00
		kmac_test_vectors_kmac	7.220s	1.115ms	50	50	100.00
		kmac_test_vectors_kmac_xof	7.600s	269.858us	50	50	100.00
V2	sideload	kmac_sideload	8.406m	19.574ms	50	50	100.00
V2	app	kmac_app	7.795m	24.776ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.371m	6.467ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.710m	136.669ms	48	50	96.00
V2	error	kmac_error	9.333m	21.565ms	49	50	98.00
V2	key_error	kmac_key_error	9.090s	5.438ms	50	50	100.00
V2	edn_timeout_error	kmac_edn_timeout_error	46.430s	1.247ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	49.900s	1.509ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	1.159m	29.417ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	46.310s	2.799ms	50	50	100.00
V2	stress_all	kmac_stress_all	49.739m	405.128ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.910s	16.422us	50	50	100.00
V2	alert_test	kmac_alert_test	0.940s	21.040us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.480s	141.969us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.480s	141.969us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.250s	48.698us	5	5	100.00
		kmac_csr_rw	1.280s	302.524us	20	20	100.00
		kmac_csr_aliasing	10.550s	1.608ms	5	5	100.00
		kmac_same_csr_outstanding	2.970s	698.480us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.250s	48.698us	5	5	100.00
		kmac_csr_rw	1.280s	302.524us	20	20	100.00
		kmac_csr_aliasing	10.550s	1.608ms	5	5	100.00
		kmac_same_csr_outstanding	2.970s	698.480us	20	20	100.00
V2		TOTAL			1039	1050	98.95
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.060s	281.683us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.060s	281.683us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.060s	281.683us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.060s	281.683us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.480s	199.266us	18	20	90.00
V2S	tl_intg_err	kmac_sec_cm	1.597m	15.280ms	5	5	100.00
		kmac_tl_intg_err	6.110s	3.864ms	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.110s	3.864ms	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	46.310s	2.799ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.481m	13.615ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	8.406m	19.574ms	50	50	100.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.060s	281.683us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.597m	15.280ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.597m	15.280ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.597m	15.280ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.481m	13.615ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	46.310s	2.799ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.597m	15.280ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	6.412m	67.093ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.481m	13.615ms	50	50	100.00
V2S		TOTAL			73	75	97.33
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.159h	498.666ms	31	50	62.00
V3		TOTAL			31	50	62.00
		TOTAL			1258	1290	97.52

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.19	98.40	93.36	99.93	95.45	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 17 failures:

Test kmac_stress_all_with_rand_reset has 17 failures.

0.kmac_stress_all_with_rand_reset.1336389947
Line 728, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 55679291498 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483744 [0x80000060]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 55679291498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.kmac_stress_all_with_rand_reset.2205546768
Line 251, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  37624808 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483672 [0x80000018]) reg name: kmac_reg_block.err_code
  UVM_INFO @  37624808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 3 failures:

Test kmac_entropy_refresh has 2 failures.

3.kmac_entropy_refresh.1890324692
Line 246, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 1268452178 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (56 [0x38] vs 126 [0x7e]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 1268452178 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

26.kmac_entropy_refresh.1636240977
Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 8669303054 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (11 [0xb] vs 58 [0x3a]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 8669303054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

35.kmac_app.4014621555
Line 385, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_app/latest/run.log

  UVM_FATAL @ 31874033510 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (242 [0xf2] vs 215 [0xd7]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 31874033510 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 3 failures:

Test kmac_test_vectors_sha3_512 has 1 failures.

13.kmac_test_vectors_sha3_512.3956051692
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/13.kmac_test_vectors_sha3_512/latest/run.log

  UVM_ERROR @ 178374920 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 178374920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_shake_256 has 2 failures.

32.kmac_test_vectors_shake_256.1838804852
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  27453722 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  27453722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.kmac_test_vectors_shake_256.3429173849
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_test_vectors_shake_256/latest/run.log

  UVM_ERROR @  73587852 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  73587852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:

Test kmac_stress_all_with_rand_reset has 1 failures.
- 18.kmac_stress_all_with_rand_reset.12295298
  Line 482, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 170056895383 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 170056895383 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Test kmac_error has 1 failures.

31.kmac_error.941515504
Line 301, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/31.kmac_error/latest/run.log

  UVM_FATAL @ 10119478538 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10119478538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

46.kmac_stress_all.3028514143
Line 304, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/46.kmac_stress_all/latest/run.log

  UVM_FATAL @ 18995550341 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 18995550341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test kmac_burst_write has 1 failures.
  - 12.kmac_burst_write.1745534439
    Line 332, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/12.kmac_burst_write/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_test_vectors_shake_128 has 1 failures.
  - 20.kmac_test_vectors_shake_128.1190548462
    Line 2188, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_test_vectors_shake_128/latest/run.log
```
  UVM_FATAL @ 5000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 5000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 5000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending 'rand_valid_o' has 1 failures:

Test kmac_stress_all has 1 failures.

5.kmac_stress_all.237957128
Line 511, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_stress_all/latest/run.log

      Offending 'rand_valid_o'
  UVM_ERROR @ 16533043351 ps: (kmac_entropy.sv:503) [ASSERT FAILED] ConsumeNotAseertWhenNotReady_M
  UVM_INFO @ 16533043351 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 5.kmac_shadow_reg_errors_with_csr_rw.930175865
    Line 246, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @   8211208 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2266127019 [0x87125aab] vs 1078051566 [0x4041c2ee]) Regname: kmac_reg_block.prefix_6 reset value: 0x0
  UVM_INFO @   8211208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_*.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 14.kmac_shadow_reg_errors_with_csr_rw.1719529743
    Line 247, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  61005258 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1760395481 [0x68ed80d9] vs 2548400406 [0x97e58116]) Regname: kmac_reg_block.prefix_0.prefix_0 reset value: 0x0
  UVM_INFO @  61005258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (kmac_test_vectors_base_vseq.sv:125) [kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (* [*] vs * [*]) Mismatch between exp_digest[*] and act_digest[*] has 1 failures:
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 25.kmac_stress_all_with_rand_reset.1290785184
    Line 459, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 77427611096 ps: (kmac_test_vectors_base_vseq.sv:125) [uvm_test_top.env.virtual_sequencer.kmac_test_vectors_kmac_vseq] Check failed exp_digest[i] == act_digest[i] (53 [0x35] vs 27 [0x1b]) Mismatch between exp_digest[52] and act_digest[52]
  UVM_INFO @ 77427611096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```