KMAC/MASKED Simulation Results

Saturday May 27 2023 07:02:22 UTC

GitHub Revision: `c06cc3921`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2359737659

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	kmac_smoke	1.583m	19.206ms	50	50	100.00
V1	csr_hw_reset	kmac_csr_hw_reset	1.170s	25.201us	5	5	100.00
V1	csr_rw	kmac_csr_rw	1.260s	36.457us	20	20	100.00
V1	csr_bit_bash	kmac_csr_bit_bash	20.330s	4.148ms	5	5	100.00
V1	csr_aliasing	kmac_csr_aliasing	11.350s	446.850us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	kmac_csr_mem_rw_with_rand_reset	2.340s	32.308us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	kmac_csr_rw	1.260s	36.457us	20	20	100.00
		kmac_csr_aliasing	11.350s	446.850us	5	5	100.00
V1	mem_walk	kmac_mem_walk	0.790s	15.206us	5	5	100.00
V1	mem_partial_access	kmac_mem_partial_access	1.470s	67.696us	5	5	100.00
V1		TOTAL			115	115	100.00
V2	long_msg_and_output	kmac_long_msg_and_output	56.043m	623.064ms	50	50	100.00
V2	burst_write	kmac_burst_write	29.163m	66.450ms	50	50	100.00
V2	test_vectors	kmac_test_vectors_sha3_224	43.276m	372.790ms	50	50	100.00
		kmac_test_vectors_sha3_256	46.217m	1.825s	50	50	100.00
		kmac_test_vectors_sha3_384	33.931m	589.608ms	50	50	100.00
		kmac_test_vectors_sha3_512	26.347m	553.093ms	50	50	100.00
		kmac_test_vectors_shake_128	1.755h	2.208s	48	50	96.00
		kmac_test_vectors_shake_256	1.524h	226.971ms	50	50	100.00
		kmac_test_vectors_kmac	7.790s	674.562us	49	50	98.00
		kmac_test_vectors_kmac_xof	7.440s	1.094ms	50	50	100.00
V2	sideload	kmac_sideload	9.055m	7.076ms	49	50	98.00
V2	app	kmac_app	7.630m	17.684ms	49	50	98.00
V2	app_with_partial_data	kmac_app_with_partial_data	6.500m	16.281ms	10	10	100.00
V2	entropy_refresh	kmac_entropy_refresh	8.179m	104.175ms	49	50	98.00
V2	error	kmac_error	8.368m	28.562ms	49	50	98.00
V2	key_error	kmac_key_error	7.920s	3.576ms	49	50	98.00
V2	edn_timeout_error	kmac_edn_timeout_error	53.320s	1.970ms	20	20	100.00
V2	entropy_mode_error	kmac_entropy_mode_error	46.110s	2.433ms	20	20	100.00
V2	entropy_ready_error	kmac_entropy_ready_error	55.700s	17.239ms	10	10	100.00
V2	lc_escalation	kmac_lc_escalation	53.040s	5.217ms	50	50	100.00
V2	stress_all	kmac_stress_all	50.952m	32.315ms	48	50	96.00
V2	intr_test	kmac_intr_test	0.890s	60.794us	50	50	100.00
V2	alert_test	kmac_alert_test	0.990s	131.310us	50	50	100.00
V2	tl_d_oob_addr_access	kmac_tl_errors	3.710s	179.387us	20	20	100.00
V2	tl_d_illegal_access	kmac_tl_errors	3.710s	179.387us	20	20	100.00
V2	tl_d_outstanding_access	kmac_csr_hw_reset	1.170s	25.201us	5	5	100.00
		kmac_csr_rw	1.260s	36.457us	20	20	100.00
		kmac_csr_aliasing	11.350s	446.850us	5	5	100.00
		kmac_same_csr_outstanding	3.050s	288.256us	20	20	100.00
V2	tl_d_partial_access	kmac_csr_hw_reset	1.170s	25.201us	5	5	100.00
		kmac_csr_rw	1.260s	36.457us	20	20	100.00
		kmac_csr_aliasing	11.350s	446.850us	5	5	100.00
		kmac_same_csr_outstanding	3.050s	288.256us	20	20	100.00
V2		TOTAL			1040	1050	99.05
V2S	shadow_reg_update_error	kmac_shadow_reg_errors	2.210s	153.213us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	kmac_shadow_reg_errors	2.210s	153.213us	20	20	100.00
V2S	shadow_reg_storage_error	kmac_shadow_reg_errors	2.210s	153.213us	20	20	100.00
V2S	shadowed_reset_glitch	kmac_shadow_reg_errors	2.210s	153.213us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	kmac_shadow_reg_errors_with_csr_rw	5.730s	2.722ms	19	20	95.00
V2S	tl_intg_err	kmac_sec_cm	1.618m	48.253ms	5	5	100.00
		kmac_tl_intg_err	6.350s	363.381us	20	20	100.00
V2S	sec_cm_bus_integrity	kmac_tl_intg_err	6.350s	363.381us	20	20	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	kmac_lc_escalation	53.040s	5.217ms	50	50	100.00
V2S	sec_cm_sw_key_key_masking	kmac_smoke	1.583m	19.206ms	50	50	100.00
V2S	sec_cm_key_sideload	kmac_sideload	9.055m	7.076ms	49	50	98.00
V2S	sec_cm_cfg_shadowed_config_shadow	kmac_shadow_reg_errors	2.210s	153.213us	20	20	100.00
V2S	sec_cm_fsm_sparse	kmac_sec_cm	1.618m	48.253ms	5	5	100.00
V2S	sec_cm_ctr_redun	kmac_sec_cm	1.618m	48.253ms	5	5	100.00
V2S	sec_cm_packer_ctr_redun	kmac_sec_cm	1.618m	48.253ms	5	5	100.00
V2S	sec_cm_cfg_shadowed_config_regwen	kmac_smoke	1.583m	19.206ms	50	50	100.00
V2S	sec_cm_fsm_global_esc	kmac_lc_escalation	53.040s	5.217ms	50	50	100.00
V2S	sec_cm_fsm_local_esc	kmac_sec_cm	1.618m	48.253ms	5	5	100.00
V2S	sec_cm_absorbed_ctrl_mubi	kmac_mubi	5.409m	23.034ms	10	10	100.00
V2S	sec_cm_sw_cmd_ctrl_sparse	kmac_smoke	1.583m	19.206ms	50	50	100.00
V2S		TOTAL			74	75	98.67
V3	throughput	kmac_throughput			0	0	--
V3	stress_all_with_rand_reset	kmac_stress_all_with_rand_reset	1.178h	626.474ms	41	50	82.00
V3		TOTAL			41	50	82.00
		TOTAL			1270	1290	98.45

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	8	100.00
V2	25	25	17	68.00
V2S	5	5	4	80.00
V3	2	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.93	98.40	93.36	99.93	93.64	96.03	98.87	98.31

Failure Buckets

UVM_ERROR (kmac_scoreboard.sv:1176) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 8 failures:

Test kmac_stress_all_with_rand_reset has 8 failures.

1.kmac_stress_all_with_rand_reset.4229670140
Line 501, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 26134584147 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483736 [0x80000058]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 26134584147 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.kmac_stress_all_with_rand_reset.1377337037
Line 348, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 12889692941 ps: (kmac_scoreboard.sv:1176) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
  UVM_INFO @ 12889692941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 4 failures:

Test kmac_test_vectors_shake_128 has 2 failures.

5.kmac_test_vectors_shake_128.1414068409
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  50909129 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  50909129 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.kmac_test_vectors_shake_128.1638128343
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_test_vectors_shake_128/latest/run.log

  UVM_ERROR @  70590646 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  70590646 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_test_vectors_kmac has 1 failures.

10.kmac_test_vectors_kmac.411764768
Line 244, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_test_vectors_kmac/latest/run.log

  UVM_ERROR @  39513208 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @  39513208 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_stress_all has 1 failures.

18.kmac_stress_all.1331922766
Line 271, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log

  UVM_ERROR @ 12426586614 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
  UVM_INFO @ 12426586614 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
- Test kmac_stress_all has 1 failures.
  - 16.kmac_stress_all.1359218368
    Line 453, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/16.kmac_stress_all/latest/run.log
```
  UVM_FATAL @ 82618692809 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 82618692809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_error has 1 failures.
  - 21.kmac_error.369040912
    Line 286, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_error/latest/run.log
```
  UVM_FATAL @ 10290181364 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 10290181364 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test kmac_stress_all_with_rand_reset has 1 failures.
  - 25.kmac_stress_all_with_rand_reset.619739913
    Line 1825, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 161454793794 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
  UVM_INFO @ 161454793794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (kmac_scoreboard.sv:1520) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:

Test kmac_entropy_refresh has 1 failures.

14.kmac_entropy_refresh.1055406384
Line 256, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest/run.log

  UVM_FATAL @ 18545380017 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (226 [0xe2] vs 242 [0xf2]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 18545380017 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test kmac_app has 1 failures.

23.kmac_app.3525004436
Line 370, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_app/latest/run.log

  UVM_FATAL @ 4543079613 ps: (kmac_scoreboard.sv:1520) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (236 [0xec] vs 105 [0x69]) Mismatch between unmasked_digest[0] and dpi_digest[0]
  UVM_INFO @ 4543079613 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: * has 1 failures:
- Test kmac_shadow_reg_errors_with_csr_rw has 1 failures.
  - 1.kmac_shadow_reg_errors_with_csr_rw.753970592
    Line 246, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest/run.log
```
  UVM_ERROR @  27532840 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (2544005232 [0x97a27070] vs 909796230 [0x363a6386]) Regname: kmac_reg_block.prefix_9 reset value: 0x0
  UVM_INFO @  27532840 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
- Test kmac_sideload has 1 failures.
  - 22.kmac_sideload.2365415817
    Line 385, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_sideload/latest/run.log
```
  UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
- Test kmac_key_error has 1 failures.
  - 34.kmac_key_error.3100292531
    Line 245, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_key_error/latest/run.log
```
  UVM_ERROR @ 413772153 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
  UVM_INFO @ 413772153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```