36c168c253| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.713m | 5.082ms | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.110s | 32.267us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.250s | 37.600us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 16.270s | 298.883us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.330s | 1.576ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.690s | 74.785us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.250s | 37.600us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.330s | 1.576ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.810s | 14.255us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.520s | 44.600us | 5 | 5 | 100.00 |
| V1 | TOTAL | 115 | 115 | 100.00 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 53.916m | 59.843ms | 49 | 50 | 98.00 |
| V2 | burst_write | kmac_burst_write | 28.862m | 43.720ms | 48 | 50 | 96.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 44.270m | 745.928ms | 50 | 50 | 100.00 |
| kmac_test_vectors_sha3_256 | 41.079m | 396.812ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_sha3_384 | 32.149m | 391.782ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_512 | 26.361m | 827.799ms | 47 | 50 | 94.00 | ||
| kmac_test_vectors_shake_128 | 1.883h | 329.280ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_256 | 1.550h | 926.036ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 10.660s | 1.427ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 8.080s | 1.836ms | 49 | 50 | 98.00 | ||
| V2 | sideload | kmac_sideload | 9.052m | 15.341ms | 49 | 50 | 98.00 |
| V2 | app | kmac_app | 7.195m | 53.381ms | 50 | 50 | 100.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 6.987m | 21.812ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 7.855m | 20.655ms | 48 | 50 | 96.00 |
| V2 | error | kmac_error | 9.022m | 5.943ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 7.160s | 3.442ms | 50 | 50 | 100.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 54.400s | 6.971ms | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 30.640s | 1.600ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 1.572m | 37.601ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 39.450s | 1.347ms | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 56.928m | 1.328s | 46 | 50 | 92.00 |
| V2 | intr_test | kmac_intr_test | 0.900s | 19.262us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.900s | 49.682us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.720s | 131.281us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.720s | 131.281us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.110s | 32.267us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 37.600us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.330s | 1.576ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.920s | 136.410us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.110s | 32.267us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.250s | 37.600us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.330s | 1.576ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.920s | 136.410us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1032 | 1050 | 98.29 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.590s | 57.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.590s | 57.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.590s | 57.498us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.590s | 57.498us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.260s | 257.328us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.045m | 33.096ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 5.110s | 585.765us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 5.110s | 585.765us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 39.450s | 1.347ms | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.713m | 5.082ms | 50 | 50 | 100.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 9.052m | 15.341ms | 49 | 50 | 98.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.590s | 57.498us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.045m | 33.096ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.045m | 33.096ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.045m | 33.096ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.713m | 5.082ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 39.450s | 1.347ms | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.045m | 33.096ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.227m | 6.438ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.713m | 5.082ms | 50 | 50 | 100.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 46.190m | 115.955ms | 17 | 50 | 34.00 |
| V3 | TOTAL | 17 | 50 | 34.00 | |||
| TOTAL | 1239 | 1290 | 96.05 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 8 | 100.00 |
| V2 | 25 | 25 | 14 | 56.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.84 | 98.10 | 92.66 | 99.89 | 94.55 | 95.91 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
1.kmac_stress_all_with_rand_reset.2226867001571069037637709187248462269308229238317938206469433834838314806038
Line 1241, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 28301467150 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 28301467150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.kmac_stress_all_with_rand_reset.7486891467932340185717338156333929426433970051883497244408704401436367002888
Line 693, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9276903054 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 9276903054 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 22 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 9 failures:
Test kmac_test_vectors_sha3_512 has 3 failures.
5.kmac_test_vectors_sha3_512.49862089456608455176086886553971529255388288828602943363462089886383140994862
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/5.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 25569025 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 25569025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.kmac_test_vectors_sha3_512.108201497705562228181694802025805058471177431446375064297034970990181075670192
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/9.kmac_test_vectors_sha3_512/latest/run.log
UVM_ERROR @ 28597425 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 28597425 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Test kmac_stress_all has 1 failures.
18.kmac_stress_all.28045542447845338064866340671263487428541152361350398147682343142299783055927
Line 329, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all/latest/run.log
UVM_ERROR @ 25462985139 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 25462985139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_sha3_384 has 1 failures.
22.kmac_test_vectors_sha3_384.29653671581983468417855675065440159583043647192908269731673298746549208593858
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/22.kmac_test_vectors_sha3_384/latest/run.log
UVM_ERROR @ 374546099 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 374546099 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
23.kmac_test_vectors_shake_256.108364206542409110063472563414459811485829573935758106983380768190489212422022
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 31448596 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 31448596 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
25.kmac_test_vectors_kmac.85209774482544313787344808927274633231969179767930997958746381958995171280569
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 147508559 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 147508559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more tests.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 7 failures:
11.kmac_stress_all_with_rand_reset.76142777366776474523176784648766020976798187375386450930849758545447512728964
Line 355, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/11.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 4167737566 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483752 [0x80000068]) reg name: kmac_reg_block.err_code
UVM_INFO @ 4167737566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.kmac_stress_all_with_rand_reset.79942297059112625376724352423532431867091710182662872537341189781038428829507
Line 1579, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/18.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 33877241484 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483688 [0x80000028]) reg name: kmac_reg_block.err_code
UVM_INFO @ 33877241484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 5 failures:
0.kmac_stress_all.8660520504024860801119762941474803982213673174622489438923104019575658724986
Line 3150, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all/latest/run.log
UVM_FATAL @ 168826747391 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 168826747391 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
29.kmac_stress_all.32650256476253325230805249494014143204297820216229012556002939406313070864649
Line 428, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/29.kmac_stress_all/latest/run.log
UVM_FATAL @ 30090828132 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 30090828132 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
14.kmac_stress_all_with_rand_reset.74613990066680746085456942715263469397594300917091271186365462142405257817690
Line 692, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/14.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 12338640004 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 12338640004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.kmac_stress_all_with_rand_reset.96705540183686250746700170206989404562399167076115688056912912050195276579335
Line 1202, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 227201705363 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 227201705363 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 4 failures:
Test kmac_burst_write has 2 failures.
1.kmac_burst_write.83994612475113060686513354647920898202460476821613642491940635990232621154624
Line 915, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/1.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
26.kmac_burst_write.75500468854779196088346486713957611293368680305712192521230848434557830753323
Line 746, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/26.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_sideload has 1 failures.
28.kmac_sideload.22204902597577907639243126106244490809287834182312684853077388184673598267444
Line 861, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_sideload/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_entropy_refresh has 1 failures.
34.kmac_entropy_refresh.75862389386268055837935356597996031040278432453046505315697379862842066566823
Line 1004, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/34.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
4.kmac_long_msg_and_output.10384672663590215611851558951112786660234476437125694411582420446918272192479
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest/run.log
Job ID: smart:b1cdbf6f-3f02-422a-bc39-24e00f6db27b
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 1 failures:
38.kmac_entropy_refresh.25197373665596694742833794843753449618680280995801301727625258453338719292703
Line 461, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/38.kmac_entropy_refresh/latest/run.log
UVM_FATAL @ 8359398432 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (171 [0xab] vs 173 [0xad]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 8359398432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---