8d1fda3660| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | kmac_smoke | 1.575m | 3.904ms | 49 | 50 | 98.00 |
| V1 | csr_hw_reset | kmac_csr_hw_reset | 1.210s | 63.938us | 5 | 5 | 100.00 |
| V1 | csr_rw | kmac_csr_rw | 1.180s | 122.623us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | kmac_csr_bit_bash | 20.070s | 5.189ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | kmac_csr_aliasing | 9.670s | 1.656ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | kmac_csr_mem_rw_with_rand_reset | 2.640s | 175.983us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | kmac_csr_rw | 1.180s | 122.623us | 20 | 20 | 100.00 |
| kmac_csr_aliasing | 9.670s | 1.656ms | 5 | 5 | 100.00 | ||
| V1 | mem_walk | kmac_mem_walk | 0.750s | 13.684us | 5 | 5 | 100.00 |
| V1 | mem_partial_access | kmac_mem_partial_access | 1.360s | 19.538us | 5 | 5 | 100.00 |
| V1 | TOTAL | 114 | 115 | 99.13 | |||
| V2 | long_msg_and_output | kmac_long_msg_and_output | 57.785m | 275.871ms | 49 | 50 | 98.00 |
| V2 | burst_write | kmac_burst_write | 27.646m | 15.288ms | 49 | 50 | 98.00 |
| V2 | test_vectors | kmac_test_vectors_sha3_224 | 43.785m | 1.356s | 49 | 50 | 98.00 |
| kmac_test_vectors_sha3_256 | 39.015m | 367.871ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_384 | 31.381m | 103.728ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_sha3_512 | 24.100m | 208.271ms | 50 | 50 | 100.00 | ||
| kmac_test_vectors_shake_128 | 1.958h | 921.779ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_shake_256 | 1.521h | 1.073s | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac | 10.190s | 1.587ms | 49 | 50 | 98.00 | ||
| kmac_test_vectors_kmac_xof | 8.720s | 876.490us | 49 | 50 | 98.00 | ||
| V2 | sideload | kmac_sideload | 8.919m | 157.583ms | 50 | 50 | 100.00 |
| V2 | app | kmac_app | 7.570m | 38.963ms | 49 | 50 | 98.00 |
| V2 | app_with_partial_data | kmac_app_with_partial_data | 7.186m | 65.760ms | 10 | 10 | 100.00 |
| V2 | entropy_refresh | kmac_entropy_refresh | 6.618m | 75.195ms | 50 | 50 | 100.00 |
| V2 | error | kmac_error | 8.883m | 21.782ms | 49 | 50 | 98.00 |
| V2 | key_error | kmac_key_error | 7.610s | 2.344ms | 49 | 50 | 98.00 |
| V2 | edn_timeout_error | kmac_edn_timeout_error | 46.000s | 575.304us | 20 | 20 | 100.00 |
| V2 | entropy_mode_error | kmac_entropy_mode_error | 45.910s | 2.433ms | 20 | 20 | 100.00 |
| V2 | entropy_ready_error | kmac_entropy_ready_error | 59.590s | 5.736ms | 10 | 10 | 100.00 |
| V2 | lc_escalation | kmac_lc_escalation | 38.830s | 638.697us | 50 | 50 | 100.00 |
| V2 | stress_all | kmac_stress_all | 29.064m | 83.371ms | 49 | 50 | 98.00 |
| V2 | intr_test | kmac_intr_test | 0.920s | 14.782us | 50 | 50 | 100.00 |
| V2 | alert_test | kmac_alert_test | 0.940s | 37.168us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | kmac_tl_errors | 3.450s | 1.401ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | kmac_tl_errors | 3.450s | 1.401ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | kmac_csr_hw_reset | 1.210s | 63.938us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.180s | 122.623us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.670s | 1.656ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.960s | 1.635ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | kmac_csr_hw_reset | 1.210s | 63.938us | 5 | 5 | 100.00 |
| kmac_csr_rw | 1.180s | 122.623us | 20 | 20 | 100.00 | ||
| kmac_csr_aliasing | 9.670s | 1.656ms | 5 | 5 | 100.00 | ||
| kmac_same_csr_outstanding | 2.960s | 1.635ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 1037 | 1050 | 98.76 | |||
| V2S | shadow_reg_update_error | kmac_shadow_reg_errors | 1.550s | 54.212us | 20 | 20 | 100.00 |
| V2S | shadow_reg_read_clear_staged_value | kmac_shadow_reg_errors | 1.550s | 54.212us | 20 | 20 | 100.00 |
| V2S | shadow_reg_storage_error | kmac_shadow_reg_errors | 1.550s | 54.212us | 20 | 20 | 100.00 |
| V2S | shadowed_reset_glitch | kmac_shadow_reg_errors | 1.550s | 54.212us | 20 | 20 | 100.00 |
| V2S | shadow_reg_update_error_with_csr_rw | kmac_shadow_reg_errors_with_csr_rw | 3.130s | 572.769us | 20 | 20 | 100.00 |
| V2S | tl_intg_err | kmac_sec_cm | 2.007m | 34.380ms | 5 | 5 | 100.00 |
| kmac_tl_intg_err | 4.930s | 233.650us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | kmac_tl_intg_err | 4.930s | 233.650us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_escalate_en_intersig_mubi | kmac_lc_escalation | 38.830s | 638.697us | 50 | 50 | 100.00 |
| V2S | sec_cm_sw_key_key_masking | kmac_smoke | 1.575m | 3.904ms | 49 | 50 | 98.00 |
| V2S | sec_cm_key_sideload | kmac_sideload | 8.919m | 157.583ms | 50 | 50 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_shadow | kmac_shadow_reg_errors | 1.550s | 54.212us | 20 | 20 | 100.00 |
| V2S | sec_cm_fsm_sparse | kmac_sec_cm | 2.007m | 34.380ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | kmac_sec_cm | 2.007m | 34.380ms | 5 | 5 | 100.00 |
| V2S | sec_cm_packer_ctr_redun | kmac_sec_cm | 2.007m | 34.380ms | 5 | 5 | 100.00 |
| V2S | sec_cm_cfg_shadowed_config_regwen | kmac_smoke | 1.575m | 3.904ms | 49 | 50 | 98.00 |
| V2S | sec_cm_fsm_global_esc | kmac_lc_escalation | 38.830s | 638.697us | 50 | 50 | 100.00 |
| V2S | sec_cm_fsm_local_esc | kmac_sec_cm | 2.007m | 34.380ms | 5 | 5 | 100.00 |
| V2S | sec_cm_absorbed_ctrl_mubi | kmac_mubi | 7.697m | 48.519ms | 10 | 10 | 100.00 |
| V2S | sec_cm_sw_cmd_ctrl_sparse | kmac_smoke | 1.575m | 3.904ms | 49 | 50 | 98.00 |
| V2S | TOTAL | 75 | 75 | 100.00 | |||
| V3 | throughput | kmac_throughput | 0 | 0 | -- | ||
| V3 | stress_all_with_rand_reset | kmac_stress_all_with_rand_reset | 1.016h | 523.293ms | 16 | 50 | 32.00 |
| V3 | TOTAL | 16 | 50 | 32.00 | |||
| TOTAL | 1242 | 1290 | 96.28 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 8 | 8 | 7 | 87.50 |
| V2 | 25 | 25 | 12 | 48.00 |
| V2S | 5 | 5 | 5 | 100.00 |
| V3 | 2 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.45 | 98.10 | 92.66 | 99.89 | 91.82 | 95.91 | 98.89 | 97.89 |
UVM_ERROR (cip_base_vseq.sv:827) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
0.kmac_stress_all_with_rand_reset.106269377374930571840217498301054339405868262272289790929864404347258079252496
Line 1140, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 74343749367 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 74343749367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.kmac_stress_all_with_rand_reset.45687363756308086488169800467670781096785154753231160357538371818087589313269
Line 1089, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 89427324025 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 89427324025 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 23 more failures.
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.intr_state.kmac_done reset value: * has 8 failures:
Test kmac_test_vectors_sha3_256 has 1 failures.
7.kmac_test_vectors_sha3_256.97446253952193484564853891263220464790162576911672805407871405008069969547129
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/7.kmac_test_vectors_sha3_256/latest/run.log
UVM_ERROR @ 39306842 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 39306842 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_smoke has 1 failures.
10.kmac_smoke.101677085358079677359542909155329193861945161537700941133128681106768310385671
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/10.kmac_smoke/latest/run.log
UVM_ERROR @ 92989145 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 92989145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_shake_256 has 1 failures.
21.kmac_test_vectors_shake_256.33987196455085262994834740343980817054997448002654785069138200543573752497611
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/21.kmac_test_vectors_shake_256/latest/run.log
UVM_ERROR @ 39600528 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 39600528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_test_vectors_kmac has 1 failures.
23.kmac_test_vectors_kmac.18826248468804135569173235517933729873911182016871289842946297959097246176713
Line 253, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_test_vectors_kmac/latest/run.log
UVM_ERROR @ 88627736 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 88627736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_error has 1 failures.
33.kmac_error.92301875727229903312052670174235228284796608288843696408662315328245869300463
Line 254, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/33.kmac_error/latest/run.log
UVM_ERROR @ 228378923 ps: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: kmac_reg_block.intr_state.kmac_done reset value: 0x0
UVM_INFO @ 228378923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more tests.
UVM_ERROR (kmac_scoreboard.sv:1175) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: kmac_reg_block.err_code has 6 failures:
8.kmac_stress_all_with_rand_reset.106156829984315722009729286363042448714082464212149199239382046458208861389083
Line 969, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 67782065133 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483648 [0x80000000]) reg name: kmac_reg_block.err_code
UVM_INFO @ 67782065133 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
20.kmac_stress_all_with_rand_reset.128723145050290803222545625976303907557682981608444329897875480543507271859
Line 505, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/20.kmac_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 11481387800 ps: (kmac_scoreboard.sv:1175) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 2147483728 [0x80000050]) reg name: kmac_reg_block.err_code
UVM_INFO @ 11481387800 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
UVM_FATAL (kmac_scoreboard.sv:218) [scoreboard] Wait EDN request has 3 failures:
28.kmac_stress_all_with_rand_reset.88855441003501558243908607823280822623715497449400011226920819065310722474531
Line 455, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/28.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 183788614919 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 183788614919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
32.kmac_stress_all_with_rand_reset.49607899176983636340212868538589865181942393368112126396171546986060827177261
Line 675, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/32.kmac_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 34910447359 ps: (kmac_scoreboard.sv:218) [uvm_test_top.env.scoreboard] Wait EDN request
UVM_INFO @ 34910447359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
Job kmac_masked-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
Test kmac_long_msg_and_output has 1 failures.
15.kmac_long_msg_and_output.15948469589042875303731088260021266001087615677043315188942309302604445156810
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest/run.log
Job ID: smart:215f8b66-264e-4348-9b43-a93c10db2a24
Test kmac_test_vectors_shake_128 has 1 failures.
25.kmac_test_vectors_shake_128.101920237638847981618901828751487428768418275237329840626069764695204340869054
Log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/25.kmac_test_vectors_shake_128/latest/run.log
Job ID: smart:32de8c5d-8315-4c27-ab92-58a6e905c487
UVM_FATAL (kmac_scoreboard.sv:1519) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] has 2 failures:
Test kmac_stress_all has 1 failures.
35.kmac_stress_all.103584316082957263888881058531563935685656963059408128648565920535268127888344
Line 327, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/35.kmac_stress_all/latest/run.log
UVM_FATAL @ 596236000 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (209 [0xd1] vs 34 [0x22]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 596236000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Test kmac_app has 1 failures.
37.kmac_app.3547065478550270779492650333605200653999704998508798287861149264667838105902
Line 729, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/37.kmac_app/latest/run.log
UVM_FATAL @ 3103734751 ps: (kmac_scoreboard.sv:1519) [uvm_test_top.env.scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (254 [0xfe] vs 208 [0xd0]) Mismatch between unmasked_digest[0] and dpi_digest[0]
UVM_INFO @ 3103734751 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 1 failures:
17.kmac_burst_write.37474397091127715087435687964618444291725113248163633224371918114921642680462
Line 1104, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/17.kmac_burst_write/latest/run.log
UVM_FATAL @ 200000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 200000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 200000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_base_vseq.sv:383) [kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == *) intr_pins[KmacErr] is not set! has 1 failures:
23.kmac_key_error.57653272406199017498658728711637824530927343482768446567986980693028917513446
Line 261, in log /container/opentitan-public/scratch/os_regression/kmac_masked-sim-vcs/23.kmac_key_error/latest/run.log
UVM_ERROR @ 1683022888 ps: (kmac_base_vseq.sv:383) [uvm_test_top.env.virtual_sequencer.kmac_key_error_vseq] Check failed (intr_pins[KmacErr] == 1) intr_pins[KmacErr] is not set!
UVM_INFO @ 1683022888 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---